K
Kees Vissers
Researcher at Xilinx
Publications - 48
Citations - 3024
Kees Vissers is an academic researcher from Xilinx. The author has contributed to research in topics: Field-programmable gate array & Artificial neural network. The author has an hindex of 18, co-authored 45 publications receiving 2176 citations. Previous affiliations of Kees Vissers include University of Kassel.
Papers
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Proceedings ArticleDOI
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
Yaman Umuroglu,Nicholas J. Fraser,Giulio Gambardella,Michaela Blott,Philip H. W. Leong,Magnus Jahre,Kees Vissers +6 more
TL;DR: FINN, a framework for building fast and flexible FPGA accelerators using a flexible heterogeneous streaming architecture that implements fully connected, convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements is presented.
Journal ArticleDOI
High-Level Synthesis for FPGAs: From Prototyping to Deployment
TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Journal ArticleDOI
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
Michaela Blott,Thomas B. Preußer,Nicholas J. Fraser,Giulio Gambardella,Kenneth O'Brien,Yaman Umuroglu,Miriam Leeser,Kees Vissers +7 more
TL;DR: The second generation of the FINN framework is described, an end-to-end tool that enables design-space exploration and automates the creation of fully customized inference engines on FPGAs that optimizes for given platforms, design targets, and a specific precision.
Proceedings ArticleDOI
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
Yaman Umuroglu,Nicholas J. Fraser,Giulio Gambardella,Michaela Blott,Philip H. W. Leong,Magnus Jahre,Kees Vissers +6 more
TL;DR: In this article, the authors present FINN, a framework for building fast and flexible FPGA accelerators using a flexible heterogeneous streaming architecture, with fully connected, convolutional and pooling layers, with per-layer compute resources being tailored to user-provided throughput requirements.
Proceedings ArticleDOI
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels
TL;DR: A comprehensive benchmark of the run-time performance and energy efficiency of a wide range of vision kernels is conducted and rationales for why a given underlying hardware architecture innately performs well or poorly based on the characteristics of arange of vision kernel categories are discussed.