T
Thomas B. Preußer
Researcher at Dresden University of Technology
Publications - 36
Citations - 486
Thomas B. Preußer is an academic researcher from Dresden University of Technology. The author has contributed to research in topics: Inference & Bytecode. The author has an hindex of 9, co-authored 35 publications receiving 339 citations. Previous affiliations of Thomas B. Preußer include Xilinx.
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Journal ArticleDOI
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
Michaela Blott,Thomas B. Preußer,Nicholas J. Fraser,Giulio Gambardella,Kenneth O'Brien,Yaman Umuroglu,Miriam Leeser,Kees Vissers +7 more
TL;DR: The second generation of the FINN framework is described, an end-to-end tool that enables design-space exploration and automates the creation of fully customized inference engines on FPGAs that optimizes for given platforms, design targets, and a specific precision.
Proceedings ArticleDOI
The embedded Java benchmark suite JemBench
TL;DR: A Java benchmark suite that enables the comparison of different embedded Java platforms while solely assuming the availability of a CLDC API, the minimal configuration defined for the J2ME, and contains benchmarks to explore multi-core/multi-threaded systems.
Proceedings ArticleDOI
Inference of quantized neural networks on heterogeneous all-programmable devices
TL;DR: In this paper, the authors describe the making of a real-time object detection in a live video stream processed on an embedded all-programmable device, where the required processing is tamed and parallelized across both the CPU cores and the programmable logic and how the most suitable resources and powerful extensions, such as NEON vectorization, are leveraged for the individual processing steps.
Proceedings ArticleDOI
Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs
TL;DR: In this paper, a generic implementation of a bit matrix compressor for Xilinx FPGAs is described, which does not require a generator tool and is agnostic of the aspect ratio of the input matrix.
Proceedings ArticleDOI
Accelerating Computations on FPGA Carry Chains by Operand Compaction
TL;DR: The carry-compact addition (CCA), a novel addition scheme that allows the acceleration of carry-chain computations on contemporary FPGA devices, is described and shown to outperform the standard RCA already for operand widths starting at 50~bits.