The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Improving resolution in photolithography with a phase-shifting mask

This paper presents Si/SiGe:C and InP/GaAsSb HBTs which feature specific assets to address submillimeter-wave and THz applications. Process and modeling status and challenges are reviewed. The specific topics of thermal and substrate effects, reliability, and HF measurements are also discussed.

Si/SiGe:C and InP/GaAsSb Heterojunction Bipolar Transistors for THz Applications

In this paper, we propose an ultrathin SiGe shell channel p-type FinFET for sub-10-nm technology nodes. Owing to the large valence band offset (VBO or $\Delta {E}_{v}$ ) between SiGe shell and Si fin, a hole quantum well is configured in the high-mobility SiGe region as the major conduction path. The proposed device is optimally designed and characterized in dc and ac. Here, high- $\kappa$ /metal gate is adopted for strong gate controllability and the high degree of freedom in threshold voltage ( ${V}_{{\text {th}}}$ ) adjustment. For a high reliability, modeling of the mobility ( $\mu$ ) and saturation velocity ( ${v}_{{\text {sat}}}$ ) is carried out for different Ge fractions ( ${x}$ ). The Eg and VBO are also determined for different ${x}$ from empirical data. With the set of modeled values and various quantum-mechanical models, the proposed device has been simulated through rigorous 3-D technology computer-aided design simulation. The designed device shows a high scalability reaching down to Lg = 5 nm. At Lg of 5 nm with a driving voltage (VDD) of −0.5 V, a current gain cutoff frequency (fT) = 368.88 GHz, dynamic power = 0.055 fJ/ $\mu \text{m}$ , and an intrinsic delay $(\tau) = 0.37$ ps are achieved. This is confirmed by the potential low-power and high-speed operations with a strong gate controllability.

Ultrathin SiGe Shell Channel p-Type FinFET on Bulk Si for Sub-10-nm Technology Nodes

Contribution: This paper brings forward a paradigm shift in microelectronic and nanoelectronic engineering education. Background: An increasing number of universities are offering graduate-level electrical engineering degree programs with multi-disciplinary Master’s-level specialization in microelectronics or nanoelectronics. The paradigm shift from electrical engineering to microelectronics graduate education has been slow, but the technology has now advanced to the point where industry is relying on cyber-physical connectivity, thus providing an opportunity for engineering education to utilize this capability. Research Questions: How are methods deployed when teaching traditional electrical engineering degrees still applicable in microelectronics education, and how are globally ranked institution shifting their online teaching and learning pedagogies for this? Methodology: A survey is presented of current trends in Master’s degree programs in microelectronics and related fields, and in electrical engineering degree programs with specialization in microelectronics. The review reveals how Quacquarelli Symonds’ top-ranked world universities, and other global universities with established micro- and nanoelectronic degrees, are selecting modules for their curricula and curricula content in attempts to attract and develop engineering students to this specialized field. Findings: The current global trend toward microelectronic education is following a part-coursework, part-dissertation Master’s degree model, consisting of several core modules, several electives, a research proposal writing module and a mini-dissertation. Furthermore, following industrial trends, there is a clear shift toward the “fabless” or cyber-physical approach and outsourced manufacturing, with technology-led teaching mediating the possibility of completing both theoretical and laboratory components using online resources and interactivity.

A Survey of Current Trends in Master’s Programs in Microelectronics

We investigated the critical dimension (CD) accuracy of 140- nm gate patterns fabricated by using the KrF phase-edge phase shifting mask (PSM), especially the dependence of the CD variation on the pattern pitch conditions, phase assignment conditions, and process conditions such as defocus and misalignment. We found that the phase assignment conditions for the neighboring 0 and 180 degree aperture pairs affected the gate width by 10 nm. The phase of apertures in the PSM should be assigned by taking the phase assignment condition of the neighboring aperture pairs into account when these aperture pairs are placed within the distance of 0.5 micrometers . The CD variation due to defocusing was found to be minimized when the Cr width of fine gate patterns in the PSM was set at 100 nm. The CD variation caused by misalignment between the PSM and the trim mask was also examined, and the trim mask generated by merging the shifter layer gave the minimum CD variation in relation to misalignment. In addition, the CD variation along the length of a fine gate pattern was examined, and the necking shape near the corners of apertures was pointed out. An additional pattern feature was evaluated to avoid it.

Precise CD control of 140-nm gate patterns using phase-edge PSM

A self-aligned SiGe HBT technology achieving a cutoff frequency $({f}_{\rm T})$ of 253 GHz was developed using a selective SiGe epitaxial growth process. Germanium concentration in an i-SiGe layer just under a ${\rm p}^{+}$ intrinsic base region was raised to 27.4% to improve ${f}_{\rm T}$ , and boron concentration in the intrinsic base region reached $2.4\times 10^{20}~{\rm cm}^{-3}$ as a deposition to maintain a breakdown voltage of 1.5 V. A 0.13- $\mu{\rm m}$ SiGe BiCMOS technology geometrically advanced from an earlier 0.18- $\mu{\rm m}$ version shrinks the emitter width from 0.2 to 0.12 $\mu{\rm m}$ to reduce collector-base capacitance and base resistance. It achieves a maximum oscillation frequency $({f}_{\rm MAX})$ of 325 GHz. This technology can be applied to optical and mm wave communication systems.

SiGe HBT Technology Based on a 0.13- $\mu{\rm m}$ Process Featuring an ${f}_{\rm MAX}$ of 325 GHz

We investigated various exposure procedures to minimize the Critical Dimension (CD) variation for the patterning of sub- quarter micron gates. To examine dependence of the CD variation on the pattern pitch and defocus conditions, the light intensity profiles of four different mask structures: (1) a binary mask with clear field, (2) a binary mask with dark field, (3) a phase-edge type phase-shifting mask (a phase-edge PSM) with clear field, and (4) a halftone phase- shifting mask (a halftone PSM) were compared, where exposure wavelength was 248 nm and numerical aperture (NA) of KrF stepper was 0.55. For 200-nm gate patterns, dependence of the CD variation on the pattern pitch and defocus conditions was minimized by a phase-edge PSM with clear field. By optimizing the illumination condition for a phase-edge PSM exposure, we obtained the CD variation of 10 nm at the minimum gate pitch of 0.8 micrometer and the defocus condition of plus or minus 0.4 micrometer. Applying the optimized exposure procedure to the device fabrication process, we obtained the total CD variation of plus or minus 27 nm.

Keiko Fukumoto

Papers

SiGe HBT Technology Based on a 0.13- $\mu{\rm m}$ Process Featuring an ${f}_{\rm MAX}$ of 325 GHz

Optimization of exposure procedures for sub-quarter-micron CMOS applications