Ken Oowada

TL;DR: A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed and the program throughput is drastically improved to twice as large as previously reported and comparable to binary memories.

TL;DR: In this article, non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages, in particular, during the programming of a selected storage element associated with a selected word line, and an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word lines and the word lines that receive the higher pass voltage.

TL;DR: The 10MB/s programming and 93ms block copy are realized by introducing 8kB page, noise-cancellation circuits, external page copy and the dual VDD scheme enabling efficient use of 1MB blocks.

TL;DR: A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time, which is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture.

TL;DR: A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time in this article, which is the first 3-bit per cell (X3) chip published with All-Bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture.