The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

Lucky-electron model of channel hot-electron injection in MOSFET'S

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

The phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied Secondary impact ionization is not responsible The responsible mechanisms are hot-electron-induced photocarrier generation and, under extreme conditions, forward biasing of the source-substrate junction The photon generation is believed to be due to the bremsstrahlung of the channel hot electrons A theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed The calculated characteristics of photon generation agree well with experimental results About 2 × 10-5photogenerated minority carriers are generated for every (primary) impact-ionization event in NMOSFET Photocarrier-induced leakage current can be fitted with either an inverse square dependence on distance or an exponential dependence with an effective decay length of about 780 µm

Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's

An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same

This silicon-carbide semiconductor device (101) has a silicon-carbide substrate (10), a main electrode (52), a first barrier layer (70a), and a wiring layer (60). The main electrode (52) is provided directly on top of the silicon-carbide substrate (10). The first barrier layer (70a) is provided on top of the main electrode (52) and is made from a conductive material that does not contain aluminum. The wiring layer (60) is provided on top of the first barrier layer (70a), is isolated from the main electrode (52) by the first barrier layer (70a), and is made from a material that does contain aluminum.

Silicon carbide semiconductor device

A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device

A time-dependent and multi-dimensional numerical modeling for semiconductor device operation is proposed, in which the quasi-Fermi potentials for electrons and holes rather than the carrier densities are directly analyzed. Fundamental equations for the quasi-Fermi potential are reduced to a diffusion equation that includes a drift term. Boundary conditions are straightforwardly derived from the device physics and are shown in a mathematically simple manner, independent of device structure complexities. From the viewpoint of numerical procedure, a combination of an implicit time integral and upwind difference scheme is adopted. The quasi-Fermi potential is a gradually changing value between the maximum and minimum external applied voltages, and the present method is suitable for numerical modeling. A time dependent and two dimensional analysis program has been developed. The advantages of the present modeling are demonstrated through the carrying out of sample calculations of, for example, MOSFET switching characteristics. Quick and stable convergence in the numerical scheme has been obtained over the range of practically used operation voltages.

A time-dependent and two-dimensional numerical model for MOSFET device operation

A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.

Semiconductor devices and their fabrication methods

A new model for hot electron emission into the oxide layer of IGFETs is presented. When IGFETs operate under high gate and drain bias conditions, electrons are accelerated by the high drain field and injected into the oxide layer at a certain probability. The present model takes into account the following: (1) the energy dependence of hot electron scattering probability, (2) the three-dimensional angle at which electrons are injected into the oxide layer, (3) the quantum effect at the SiSiO 2 interface that gives the reflection probability, and (4) the scattering and reaching probabilities without energy loss. The total emission current is obtained by a five-fold integral over the energy, position and solid angle elements. The current thus predicted is expected to be two or three orders of magnitude smaller than that from Phillips' model previously proposed for IGFET emission current and hence closer to experimintal data. The present model can give the position dependence of emitted current and is suitable for incorporation into two-dimensional numerical analysis.

IGFET hot electron emission model

Operation mechanisms of devices with electrically floating regions have been analyzed by device simulations. An insulator has been modeled as a wide-gap semiconductor and the device simulation has been carried out in the whole region including insulator and floating regions. By using this approach, we have evaluated electrical properties of the capacitances used to represent such devices; i.e., the capacitance of interconnect structures with metal-fill and the drain capacitance of an advanced SOI–MOSFET with an electrically floating interlayer. When one-fourth of an insulating area between parallel interconnect-lines is occupied by a squared fill, the capacitance between the lines was found to increase by three-fourths, over the value for a parallel plate capacitance without dummy fills. Also, the drain capacitance of an advanced SOI–MOSFET structure, i.e., a Si/oxide/poly-Si/oxide/Si-substrate, was analyzed. When the doping concentration of the electrically floating poly-Si interlayer is not so high, the interlayer is partially depleted and a depletion capacitor is formed. The floating potential varies non-linearly with the applied bias and is smaller than the bias. The total capacitance of a multi-oxide-layered SOI–MOSFET structure is much lower than the MOS capacitance estimated from the oxide thickness. Floating elements have great advantages in terms of decreasing capacitance values.

Ken Yamaguchi

Papers

Controllable conduction device

A time-dependent and two-dimensional numerical model for MOSFET device operation

Semiconductor devices and their fabrication methods

IGFET hot electron emission model

Capacitance analysis of devices with electrically floating regions