An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same

An assembly includes a first electrical circuitry for providing a first electrical signal containing data and a transmitting arrangement, connected with the first electrical circuitry, for receiving the first electrical signal and for converting the first electrical signal into an electromagnetic signal containing at least a portion of the data. The electromagnetic signal has a carrier frequency greater than 300 GHz. The assembly also includes a receiving arrangement for receiving the electromagnetic signal and for converting the electromagnetic signal into a second electrical signal containing at least some of the portion of the data, and a second electrical circuitry connected with the receiving arrangement and configured for receiving the second electrical signal.

Terahertz interconnect system and applications

A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be captured and, hence, to store desired multi-value data while preventing the occurrence of an inconvenience such as data corruption.

Multi-level type nonvolatile semiconductor memory device

Devices and techniques for integrating a silicon superlattice optical modulator on a silicon substrate with other circuit elements. The superlattice structure is designed to convert the indirect bandgap structure of silicon into a direct bandgap structure to achieve more efficient optical absorption. The modulator can be fabricated based on a structure of a circuit element by using standard fabrication processes for silicon integrated circuits such as metal oxide semiconductor processing.

Integrated semiconductor superlattice optical modulator

Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the quantum dots supported on the solid substrate, the quantum dots do not aggregate when dispensing a paste obtained by mixing the quantum dots with a paste resin for use in packaging of a light emitting diode. Thereby, a light emitting diode able to maintain excellent light emitting efficiency can be manufactured.

Quantum dot phosphor for light emitting diode and method of preparing the same

A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device

A semiconductor logic element is provided which is capable of a plurality of logic operations. The semiconductor logic element includes a semiconductor substrate on which is disposed at least three control electrodes and an output electrode for outputting signals in response to inputs to said control electrodes, making it possible to significantly reduce the number of elements constituting a logic circuit and to provide high speed processors and electronic computers. Logic circuitry and apparatus using the semiconductor logic elements are also provided.

Semiconductor logic element and apparatus using thereof

A controllable conduction device comprises an upstanding pillar structure (20) having a side wall (22) and a top surface (21), the structure being formed of regions (6, 7) of relatively conductive and non-conductive material such that in a first condition, charge carrier flow can occur through the pillar structure and in a second condition the regions present a tunnel barrier configuration that inhibits charge carrier flow, and a side gate (23) structure alongside the side wall (22) of the pillar structure, configured to apply an electric field through the side wall into the pillar structure to control charge carrier transport. The device can be used as a memory with a memory node (10) beneath the pillar structure, which stores charge that passes from a control electrode (11) on the top surface (21) of the pillar structure. The device can also be configured as a transistor with a source (5) on top of the pillar and a drain (2) underlying it.

Controlled conduction device

A controlled conductivity device includes a barrier structure (3)
formed of regions of relatively conductive (11,13,11',13') and
non-conductive material (10,12) such that in a first condition, charge
carrier flow can occur through the structure and in a second condition
the regions present a tunnel barrier configuration that inhibits charge
carrier flow through the structure, an output region (2) to receive
charge carriers that pass along a path through the structure, and an
input region (6) for supplying charge carriers to the path so as to pass
through the structure to the output region, wherein the regions of
non-conductive material are configures so as to provide an energy band
profile that comprises guard barrier components (14,16) adjacent the
input and output regions respectively, and a main barrier component (15)
between the guard barrier components, the main barrier component having
a width (w') of 2nm or more, the guard barrier components having a width
(w) of 3nm or less and the barriers being spaced apart by 45nm or
less, or when the main barrier component has a width of 6nm or more, the
barriers are spaced apart by 20nm or less. The device can be used as a
memory in which case the output region (2) comprises a memory node to
store charge, or as a transistor, in which case the input an output
regions comprise a source and drain for charge carriers. A side gate (9)
is provided to control current flow.

Controllable solid-state device comprising a tunnel barrier structure

In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with a thin insulating film in between. This conductive film (1.11') is electrically connected to a lower electrode (1.11) of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.

Tatsuya Teshima

Papers

Controllable conduction device

Semiconductor logic element and apparatus using thereof

Controlled conduction device

Controllable solid-state device comprising a tunnel barrier structure

Semiconductor memory device having a long data retention time with the increase in leakage current suppressed