Showing papers in "Solid-state Electronics in 2004"

Multiple-gate SOI MOSFETs

Abstract: In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and the emergence of a new class of MOSFETs, called triple-plus (3 + )-gate devices offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOSFET.

Complementary tunneling transistor for low power application

Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

AC performance of nanoelectronics: towards a ballistic THz nanotube transistor

Abstract: We present phenomenological predictions for the cutoff frequency of carbon nanotube transistors. We also present predictions of the effects parasitic capacitances on AC nanotube transistor performance. The influence of quantum capacitance, kinetic inductance, and ballistic transport on the high-frequency properties of nanotube transistors is analyzed. We discuss the challenges of impedance matching for ac nano-electronics in general, and show how integrated nanosystems can solve this challenge. Our calculations show that carbon nano-electronics may be faster than conventional Si, SiGe, GaAs, or InP semiconductor technologies. We predict a cutoff frequency of 80 GHz/L, where L is the gate length in microns, opening up the possibility of a ballistic THz nanotube transistor.

Thermal annealing effects on Ni/Au based Schottky contacts on n-GaN and AlGaN/GaN with insertion of high work function metal

Abstract: Recent progress in GaN based high electron mobility transistors (HEMTs) has revealed them to be strong candidates for future high power devices with high frequency operation. In order to extract and utilize the favorable GaN material properties, however, there is still a lot to be investigated. Reduction of the gate leakage current is one of the key issues to be solved for their further improvement. A high work function metal such as Pt, Ir, Pd or Mo was inserted to the conventional Ni/Au Schottky contact to n-GaN and AlGaN/GaN epilayers, and the Schottky diodes were studied in detail with respect to the thermal annealing in nitrogen ambient. The electrical characteristics were found to be changed by the thermal treatment in each device. A drastic improvement was attained in the Ni/Pt(Ir)/Au system whereas degradation occurred in Ni/Mo/Au by RTA at 500 °C for 5 min. These phenomena were confirmed to be dependent on the work function of each inserted metal. The role of Ni in the Ni/Pt/Au system was also investigated, and it was found to be essential in obtaining better electrical performance in comparison with the diodes without Ni, such as Pt/Au or Ir/Au Schottky electrodes. The AlGaN/GaN HEMTs were fabricated using Ni/Pt/Au gate contacts. Reduction of the gate leakage current by as much as four orders of magnitude was successfully recorded by thermal annealing without degrading the transconductance of the transistor, and it was concluded that this technique was promising for high power AlGaN/GaN HEMT electronics.

Device modeling and simulation of the performance of Cu(In1−x,Gax)Se2 solar cells

Abstract: Device modeling and simulation studies of a Cu(In1� x,Gax)Se2 (CIGS) thin film solar cell have been carried out. A variety of graded band-gap structures, including space charge region (SCR) grading, back surface region grading, and double grading of the CIGS absorber layer, are examined. The device physics and performance parameters for different band-gap profiles were analyzed. Based on the simulation results, an optimal graded band-gap structure for the CIGS solar cell is proposed. The performance of the optimally graded band-gap cell is superior to that of the uniform bandgap cell. The SCR grading of the CIGS absorber layer improves the open-circuit voltage (Voc) without significantly sacrificing the short-circuit current density (Jsc) compared to the uniform band-gap CIGS. The back surface grading enhances both Voc and Jsc. An optimal graded band-gap profile, such as a double grading consisting of the SCR grading and back surface grading, improves significantly the efficiency up to 19.83% AM1.5G compared to the uniform bandgap profile with 15.42% efficiency. A comparison of the simulation results with published data for the CIGS cells shows an excellent agreement of photo-current density–voltage and quantum efficiency characteristics. � 2003 Elsevier Ltd. All rights reserved.

Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques

Abstract: Techniques for fabricating strained Si, SiGe, and Ge on-insulator include SIMOX, Ge condensation and wafer bonding. In this paper, a brief introduction of each method is presented, with a detailed discussion of wafer bonding approaches for strained Si, SiGe, and Ge on-insulator. Wafer bonding with stop layers is found to be the most general approach with the ability to create ultra-thin layers of strained Si, SiGe, and Ge on-insulator with low threading dislocation densities and precise control over layer thickness.

Theoretical limit estimation of lateral wide band-gap semiconductor power-switching device

Abstract: The theoretical limit of a lateral wide band-gap semiconductor (WBS) power device was estimated for SiC, GaN and diamond. The lateral WBS device realizes ultra-low on-resistance due to a very short gate-drain offset, and a power integration circuit with very high power can be easily realized even with a small chip. The lateral WBS devices with breakdown voltage of over 1 kV realized on-resistance below 1 mΩ cm2. For the breakdown voltage of over 10 kV, diamond devices are attractive due to the large critical field (5.6 MV/cm). Although the WBS device realizes drastic reduction of both the chip area and the power loss, the heat dissipation technique and high current density switching capability are also important for bringing out the potential of the WBS device.

Low-energy plasma-enhanced chemical vapor deposition for strained Si and Ge heterostructures and devices

Abstract: We review the potential of low-energy plasma-enhanced chemical vapor deposition (LEPECVD) for the fabrication of strained Si and Ge heterostructures and devices. The technique is shown to be equally applicable to the formation of relaxed SiGe buffer layers, and to entire heterostructures including strained modulation doped channels. Pure Ge channels on Ge-rich linearly graded buffers are shown to exhibit low-temperature hole mobilities up to 120,000 cm 2 V � 1 s � 1 , limited by remote impurity and background impurity scattering rather than interface roughness scattering. Strained-Si modulation-doped field-effect transistors (n-MODFETs) with excellent frequency response have been fabricated by combining LEPECVD and MBE for buffer layer and active layer growth, respectively. Maximum oscillation frequencies of n-MODFETs above 140 GHz have been achieved for active layer stacks both on buffers linearly graded to a Ge fraction of 40% at a rate of 10% per micron, and on constant composition buffers which are 10 times thinner. The use of a thin buffer results in significantly less device self-heating. � 2004 Elsevier Ltd. All rights reserved.

Engineering strained silicon on insulator wafers with the Smart CutTM technology

Abstract: Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the Smart CutTM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a “semiconductor on insulator” structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator (“SGOI”) substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented.

Polyaniline/single-walled carbon nanotube composite electronic devices

Abstract: Composites of high molecular weight polyaniline (PANI) and various weight percentages of single-walled carbon nanotubes (SWNT) were fabricated using solution processing. Electrical characteristics of metal–semiconductor (MS) devices fabricated from the PANI/SWNT composites were studied. Current–voltage (I–V) characteristics of these devices indicate a significant increase in current with an increase in carbon nanotube concentration in the composite. The dominant transport mechanisms operating in these devices were investigated by plotting the forward I–V data on a log–log scale, which revealed two power-law regions with different exponents. In the lower voltage range, the exponent is approximately 1, implying that the charge transport mechanism is governed by Ohm's law. The charge transport mechanism in the higher voltage range, where the exponent varies between 1.1 and 1.7, is consistent with space-charge-limited (SCL) emission in the presence of shallow traps. The critical voltage (Vc), which characterizes the onset of SCL conduction, decreases with increasing SWNT concentration. In addition, Vc was observed to increase with temperature. These initial results indicate that with further improvements in material consistency and reduction in defect densities, the polyaniline/single-walled carbon nanotube composite material can be used to fabricate organic electronic devices leading to many useful applications in microelectronics.

A process/physics-based compact model for nonclassical CMOS device and circuit design

Abstract: A process/physics-based compact model (UFDG) for nonclassical MOSFETs having ultra-thin Si bodies (UTB) is overviewed. The model, in essence, is a compact Poisson–Schrodinger solver, including accountings for short-channel effects, and is applicable to nanoscale fully depleted (FD) SOI MOSFETs as well as generic double-gate (DG) devices. The utility of UFDG in nonclassical CMOS device design, as well as circuit design, is stressed, and demonstrated by using it in Spice3 to design UTB MOSFETs and to project extremely scaled DG and FD/SOI CMOS performances. Also, calibration of UFDG to fabricated FinFETs yields new physical insights about these potentially viable nanoscale DG devices, and about model requirements for them.

Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications

Abstract: An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in double gate (DG) silicon-on-insulator (SOI) MOSFETs. Based on modeling, 2D simulation and experimental results, we show DG MOSFETs with laterally asymmetric channel engineering can achieve high values of saturation drain current, exceptionally high values of Early voltage (> 1600 V) and intrinsic DC gain of 70-80 dB for L-eff = 1.64 mum, well in excess of those reported so far. Results of GC DG MOSFETs have also been compared with experimental and simulated data of uniformly doped double and single gate (SG) SOI MOSFETs. The analysis takes into account the effect of length and doping of the high and low doped regions to develop a compact model suitable for device design. The results of analytical model agree well with experimental and simulation data. We propose design guidelines for overall optimum performance of GC DG MOSFETs for realizing future high performance analog circuits. (C) 2004 Elsevier Ltd. All rights reserved.

Reliability of SiC MOS devices

Abstract: Fundamental limitations to oxide reliability are analyzed in silicon carbide based devices. A barrier height primarily determined by band offsets between metal/SiC and the dielectric, and the electric field in the dielectric results in tunneling current into the dielectric, resulting in its degradation. Since band offsets for SiC to most dielectrics are smaller than those with respect to Si, a lower reliability is expected for SiC-dielectric based devices as compared to Si MOS devices. Other researchers have correlated interface states in the SiC–oxide as tunneling sites that increase gate leakage currents and influence the barrier to tunneling. Depending on the allowed maximum electric field in the gate oxide, there exists a trade-off between on-state resistance and SiC MOS reliability.

Fabrication of ZnO-based metal-insulator-semiconductor diodes by ion implantation

Abstract: A ZnO-based metal–insulator–semiconductor junction has been fabricated using an isolation layer fabricated by N+ ion implantation. I–V dependences show a good rectifying diode-like behavior with a low leakage current of 10−6 A and a threshold voltage of about 3 V. Ultraviolet light emission under forward bias exhibits a wavelength maximum of 388 nm and a full width at half maximum of 128 meV at room temperature.

Investigation of defect properties in Cu(In,Ga)Se2 solar cells by deep-level transient spectroscopy

Abstract: The performance of the chalcopyrite material Cu(In,Ga)Se 2 (CIGS) used as an absorber layer in thin-film photovoltaic devices is significantly affected by the presence of native defects. The deep-level transient spectroscopy (DLTS) technique is used in this work to characterize the defect properties, yielding relevant information about the defect types, their capture cross-sections, and energy levels and densities in the CIGS cells. Three solar cells developed using different absorber growth technologies were analyzed using DLTS, capacitance–voltage ( C – V ), and capacitance–temperature ( C – T ) techniques. It was found that CIS cells grown at the University of Florida exhibits a middle-gap defect level that may relate to the cell's low fill factor and open-circuit voltage values observed. A high efficiency ( η c >18%) CIGS cell produced by the National Renewable Energy Laboratory (NREL) was found to contain three minority-carrier (electron) traps and a 13% CIGS cell produced by the Energy Photovoltaics Inc. (EPV) exhibited one majority (hole) trap. The approach followed using the DLTS technique serves as a paradigm for revealing the presence of significant defect levels in absorber materials, and may be used to support the identification of remedial processing operations.

Coupling effects and channels separation in FinFETs

Abstract: Double-gate devices are best candidates for the MOSFET scaling down to the deca-nanometer range. The motivation of this work is to investigate the coupling effects in FinFETs and to extract the carrier mobility in each of the four possible channels. The coupling of the lateral, front and back interfaces is analyzed based on experimental results in FinFETs with various geometries. The influence of the substrate bias on the front and lateral surface potentials is especially emphasized. The back-gate action is minimized in ultra-narrow fins. Finally, the transport properties at each interface are presented and compared. The electron and hole mobilities are significantly lower on the fin edges than at the top and bottom interfaces.

Smart-Cut® technology: from 300 mm ultrathin SOI production to advanced engineered substrates

Abstract: The Smart-Cut® process, based on hydrogen implantation and wafer bonding, is a generic thin layer process transfer. Unibond® SOI wafers are today in volume production, showing that splitting and bonding steps can be controlled, with high yields. Taking advantage of standard equipments flexibility, the process has been successfully scaled up to 300 mm. Most advanced 200 mm processes were successfully transferred to 300 mm, with wafers showing uniformity and defectivity results compatible with industry requirements for fully depleted device applications. The number of wafer solutions offered by the Smart-Cut® technology is already much greater than just SOI. Strained silicon on insulator, silicon on quartz (SOQ), single crystal silicon layer on plastic supports, silicon carbide on insulator, germanium on insulator, multilayer SOI structures are just few examples of the potential of Smart Cut® to engineer and design new substrates to answer the demands of the industry. A review of the progress achieved is given.

Silicon nanocrystal based memory devices for NVM and DRAM applications

Abstract: Si nanocrystal based devices have shown potential in reducing the operating voltages used in continuous floating gate FLASH devices. We discuss the critical aspects of this technology––nanocrystal formation by CVD, nanocrystal passivation, and HCI/FN mode of operation of non-volatile memory bitcells fabricated using a 0.13 μm CMOS process technology. The superior FN erase characteristics of nanocrystal memory compared to a SONOS device are demonstrated, which enables the use of thicker tunnel oxides in nanocrystal memory devices as required to mitigate READ disturb. It is shown that nanocrystal area coverage of

60Co gamma radiation effects on DC, RF, and pulsed I–V characteristics of AlGaN/GaN HEMTs

Abstract: Total-dose gamma radiation effects on static, high-frequency, and pulsed current–voltage characteristics of silicon nitride passivated AlGaN/GaN HEMTs were investigated. Passivated AlGaN/GaN HEMTs were exposed to a maximum total dose of 600 Mrad using a 60Co source under nitrogen ambient. The magnitude of the changes in the DC characteristics exhibited a monotonic increase with increasing radiation dose. At 600 Mrad dose, −0.1 V shift in threshold voltage and 3% increase in maximum transconductance was observed. High-frequency small-signal characteristics did not exhibit a significant change. Pulsed current levels increased in relation to the shift in threshold voltage, indicating no radiation damage related degradation in large signal transient behavior. The mobility, sheet carrier density, contact resistance, and sheet resistance of the sample did not exhibit measurable changes. The limited response of the devices to the high radiation dose indicates that the AlGaN/GaN HEMTs can have very high radiation hardness. The observed effects are consistent with radiation-induced trap creation.

AlGaN/GaN HEMT based liquid sensors

Abstract: An AlGaN/GaN high electron mobility transistor structure was used for sensing different liquids present in the gate region. The forward current showed significant decreases upon exposure of the gate area to solvents (water, acetone) or acids (HCl). The pH sensitivity is due to changes in net surface charge that affects the relative depletion in the channel of the transistor. The results indicate that nitride-based heterostructures may have application in integrated chemical, gas and fluid monitoring sensors.

Mesostructured SnO2 as sensing material for gas sensors

Abstract: Mesostructured tin oxide with high specific surface area was synthesized using a cationic surfactant (cetyltrimethylammonium bromide, CTAB: CH3(CH2)15N+(CH3)3Br−) as the organic template and the hydrous tin chloride (SnCl4 · 5H2O) and NH4OH as the inorganic precursor and alkali source under acidic conditions at ambient temperature. The surface areas of mesostructured tin oxides are about 368, 343 and 134 m2/g for calcination at 300, 350 and 400 °C, respectively. The tin oxides used as sensitive materials of indirect heating structure sensors were fabricated on an alumina tube with Au electrodes and platinum wires. Electrical and sensing properties of the sensors based on mesostructured tin oxide were investigated. It was found that the materials with high surface area had higher sensitivity to C2H5OH and H2 and selectivity to other interferential gases (such as methane, butane, CO and gasoline) than commercial sample of polycrystalline tin (IV) oxide.

Electrical analysis of external mechanical stress effects in short channel MOSFETs on (0 0 1) silicon

Abstract: This paper presents an electrical analysis of external mechanical stress effects on devices characteristics for long and short channel MOSFETs in advanced 0.13 μm technology. Similar bulk and SOI generations for nMOS and pMOS devices are studied. By applying external calibrated stress we measure piezoresistive effects and compare small and long transistors electrical responses. Main results are that the threshold voltage (Vt) variations were shown negligible whereas mobility dependence with stress was the most significant effect. After the parasitic series resistance (Rsd) correction on short devices, we extracted comparable piezoresistive coefficients on short and long devices indicating that 2D or local effects can be neglected in all cases. Comparison bulk/SOI showed slightly higher piezoresistive coefficients for SOI. Finally, measurement errors were estimated.

Integral function method for determination of nonlinear harmonic distortion

Abstract: The analysis of harmonic distortion is of prime importance for the analog and mixed integrated circuits. Recently we presented a new integral function method (IFM), based on a completely new principle, which allows the calculation of harmonic distortion using the DC output characteristic of devices or circuits. In this work we complement the integral function method to provide direct calculation of the following distortion figures: total harmonic distortion (THD), second harmonic distortion (HD2) and third harmonic distortion (HD3), voltage intercept points (VIP) and the intermodulation distortion (IMD). The comparison with the same distortion figures calculated by the Fourier coefficients (FC), by direct AC measurements and from FFT in simulators, indicates that results obtained by IFM give an excellent agreement in the full range of the analyzed active regions. The IFM combines simplicity and computer efficiency with accuracy and with the possibility to easily analyze the distortion when varying any of the circuit or device parameters.

Silicon nanocrystal memory devices obtained by ultra-low-energy ion-beam synthesis

Abstract: Si-nanocrystal memory devices aiming at low-voltage non-volatile memory applications are explored. The devices consist of a single metal-oxide-semiconductor field-effect-transistor with silicon nanocrystals fabricated through ultra-low-energy (1 keV) Si implantation of the gate oxide (7 nm in thickness) and subsequent thermal annealing. Process issues like boron contamination and parasitic currents that affect the threshold voltage and transfer characteristics of the intended devices are discussed in terms of device structure, process parameter and device simulation. It is shown that these issues can be overcome under appropriate process modifications. Threshold shift of about 2 V are obtained for a 10 ms +9 V/−9 V pulse regime where both electron and hole trapping occur. Neither degradation, nor drift in memory window is detected after 1.5 × 10 6 10 ms +9 V/−9 V cycles. Charge retention measurements reveal that the de-trapping mechanism of stored holes is faster than that of trapped electrons and independent on the temperature. Memory operation with reduced hole trapping, herein demonstrated for a 10 ms +9 V/−7 V regime leading to a 0.3 V 10-year extrapolated memory window at 150 °C, should be preferred for long non-volatile retention of years.

Negative Schottky barrier between titanium and n-type Si(0 0 1) for low-resistance ohmic contacts

Abstract: A metal–semiconductor contact should have a negative Schottky barrier if the metal has a work function less than the electron affinity of the semiconductor. Such a contact would behave ohmically with a low internal resistance. In reality, the electronic states on the semiconductor surface pin the surface Fermi level and make almost all the metals to show a positive Schottky barrier. By eliminating surface states on Si(0 0 1) with a monolayer of selenium, ohmic contacts with a negative Schottky barrier are demonstrated between titanium and n-type Si(0 0 1). These contacts are found to be thermally stable up to 400 °C.

Strained Si on insulator technology: from materials to devices

Abstract: SiGe-free strained Si on insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced capacitance and improved scalability of thin film silicon on insulator (SOI). We demonstrate fabrication of 20% Ge equivalent strain level SSOI substrates with Si thicknesses of 100 and 400 A by hydrogen-induced layer transfer of strained Si layers from high quality graded SiGe virtual substrates. The substrate properties are excellent: wafer scale strained Si film thickness uniformities are better than 8%, strained Si surface roughnesses are better than 0.5 nm RMS, and robust tensile strain levels are maintained during anneals as long as 80 min at 1100 °C. Fully depleted n-MOSFET electrical results show that biaxial tensile strain, and hence enhanced mobility, is fully maintained in the 400 A 20% SSOI films through the substrate and device fabrication processes, even after a generous FET fabrication thermal budget. Long channel devices exhibit nearly ideal subthreshold slopes of 66 mV/decade and exhibit 112% electron mobility enhancements at Ninv=1×1013 cm−2, identical to devices on bulk strained Si substrates. Furthermore, a photoemission microscopy study was used to confirm that the useable SSOI layer thickness significantly exceeds the critical thickness for fabrication of bulk strained Si FETs without deleterious leakage current effects. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator is an ideal platform for future generations of Si-based microelectronics.

Requirements for ultra-thin-film devices and new materials for the CMOS roadmap

Abstract: For the first time various devices architectures (bulk, SOI and SON) and process modules (metal gate, strained-Si channel) are compared in a consistent way using the same analytical tool. This analysis shows on one hand that the conventional bulk cannot match the requirements throughout the entire ITRS’01 roadmap, but on the other hand it gives clear guidelines on device architectures permitting to do so. In other words, this paper puts forward a device architecture roadmap and shows precisely which architectures, modules and materials will be needed at a given CMOS node. This message analysis may be of importance for semiconductor manufacturers, equipment makers and SOI wafer providers.

The super junction bipolar transistor: a new silicon power device concept for ultra low loss switching applications at medium to high voltages

Abstract: A new silicon power device concept based on the super junction (SJ) principle for power electronics in a broad spectrum of consumer, industrial and other energy conversion applications is presented in this paper. This new concept can help to sustain the trend towards ultra low loss switching––the past, present and future dominant driving force in the development of silicon high power switches. The super junction bipolar transistor (SJBT) shares many similarities with the super junction MOSFET. It has a similar MOS control structure integrated on the cathode side on top of a base region, which is organized into a columnar structure of alternating p- and n-doped pillars. The anode consists of a p-doped emitter––the SJBT is thus a bipolar super junction power device with carrier modulation taking place in only some portion of the base. The super junction structure makes up for fundamentally different device characteristics compared to an IGBT: carrier modulation in the SJBT is made possible by elimination of the reverse bias between p- and n-doped pillars when large quantities of majority carriers are injected from the p-emitter into the p-type pillar. With the electrostatic potential being grounded at the cathode, de-biasing of the pillars as well as carrier modulation will vanish towards the cathode. The unique characteristic of the SJBT on-state is an electron–hole plasma originating at the anode, which will segregate and give place to unipolar current flow in both pillars (de-mixing of the plasma) in the base region close to the cathode. Compared to an IGBT, the SJBT offers the same or lower conduction losses at a very small fraction (25%) of the cost in terms of switching losses.

Prediction study of elastic properties under pressure effect for zincblende BN, AlN, GaN and InN

Abstract: We have performed a first-principles full-potential augmented-plane wave plus local orbitals (FP-APW+lo) calculations with density functional theory in local density approximation, in aim to determine and predict the pressure dependence of elastic constants of BN, AlN, GaN and InN compounds. From our results, we sustain the idea of no evidence that the soft acoustic mode is responsible for the phase transition.

Two-dimensional simulation of pattern-dependent oxidation of silicon nanostructures on silicon-on-insulator substrates

Abstract: Pattern-dependent oxidation (PADOX) of silicon nanostructures fabricated on silicon-on-insulator (SOI) substrates is simulated. In order to reproduce the characteristic features of PADOX in the simulation, the volume expansion due to silicon oxidation is treated as a dilational strain, and the strain is applied to a transition region in which silicon is converted to oxide. In addition, the silicon oxide and transition layer are treated as viscoelastic solids, and the stress dependencies of the oxidation reaction, oxygen self-diffusion in the oxide, and oxide viscosity are taken into account. The simulated silicon and oxide shapes after oxidation satisfactorily reproduce the experimental results. The simulation results suggest that the rounded silicon shapes that appear after oxidation are mainly caused by the stress-induced reduction of oxide viscosity. Moreover, we obtain oxidation-induced strain and stress from the simulation. Based on the strain obtained, the electron potential profile responsible for the operation of single-electron transistor (SET) is investigated. The compressive strain in the silicon wire region of SETs reduces the bandgap, and this reduction is critical for the formation of the potential profile responsible for SET operation.