An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Flash EEprom system

In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a non-volatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.

Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6T) SRAM and proposes an alternative bitcell that functions too much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.

A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.

Nanoscale CMOS

We demonstrate a new MOSFET on ultra-thin BOX that allows wide-range back-bias control in low-power and high-performance applications. The back gate is effective not only to increase the drive current by about 20% in active mode but also in reduce the off-current by an order of magnitude in stand-by mode. We have also demonstrated tunable-threshold-voltage technology for devices with metal gates and ion implantation for V/sub th/ control. The target V/sub th/ for low-power applications was achieved by using ion implantation for V/sub th/ control. We propose a 6-transistor SRAM memory cell in which we obtain even more benefit from the new device structure by adding a feedback mechanism. A proposed 6-Tr SRAM memory cell is shown to dramatically improve SNM characteristics at the 65-nm technology nodes, and this effect will also apply at finer nodes.

Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

We have developed the new "Yin-Yang" feedback technology for SRAM cells. This technology is applied to six-transistor cells and four-transistor cells, which are composed of transistors with the new D2G-SOI structure. At the 65-nm process node, these cells can operate at 0.7 V in mass-produced LSIs under real usage conditions. Max operating speeds are 300 MHz for the six-transistor and 200 MHz for the four-transistor cell. Leakage current of the four-transistor cell is about 1/1000 that of a conventional four-transistor cell. These cells provide a SRAM menu that allows us to optimally balance the requirements of various types of SRAM in low-power LSIs.

Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

Multi-layered structure having single crystalline semiconductor film formed on insulator

After desired impurities are diffused into a semiconductor substrate through a masking layer of SiO2 formed thereupon so as to form a semiconductor device, the masking layer is completely removed therefrom and thereafter more than two thin layers of different insulating materials are deposited upon the cleaned surface of the semiconductor device thus providing a method of forming a semiconductor device with an improved passivation film thereon. Said insulating materials are selected from the group consisting of silicon dioxide, a silicon nitride, alumina, boro-silicate glass, phospho-silicate glass, alumino-silicate glass, alumino-phospho-silicate glass and alumino-boro-silicate glass, and the thickness of each thin layer is in the range of 300 to 1500 angstroms and the first layer is silicon dioxide.

Semiconductor device having controlled surface charges by passivation films formed thereon

Disclosed is a method of manufacturing a semiconductor device capable of improving the reliability of the semiconductor device, which has a field effect transistor having a source-drain structure with a shallow junction. In the process for realizing the reduction of the resistance in a diffusion layer for a source and drain with a shallow junction, in which a part of an amorphous layer formed by the ion implantation for forming a diffusion layer for a source and drain is selectively melted and recrystallized by the use of laser irradiation, in order to prevent the occurrence of defects such as short circuit at a portion where a region to be melted and a gate electrode are overlapped with each other, ion implantation is performed after the formation of a first gate sidewall insulator on a sidewall of the gate electrode so as to obtain a structure in which the amorphous layer is not overlapped with the gate electrode. In this manner, it is possible to melt and recrystallize the amorphous layer without causing the defects such as short circuit.

Masatada Horiuchi

Papers

Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control

Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

Multi-layered structure having single crystalline semiconductor film formed on insulator

Semiconductor device having controlled surface charges by passivation films formed thereon

Semiconductor device and process for forming same