The anomalous leakage current I L in LPCVD polysilicon MOSFET's is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce I L , and indicates when the back-surface leakage component is significant.

Anomalous leakage current in LPCVD PolySilicon MOSFET's

Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

In an active matrix display device, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shaped semiconductor region, is used as a switching element. Each of the TFT have offset regions and lightly doped drain (LDD) regions. Then, by supplying a selection signal to the gate lines, the TFTs are operated, thereby writing data to the pixel, while a suitable voltage is supplied to the capacitance line, a channel is formed thereunder and it becomes a capacitor. Thus the amount of discharge from the pixel electrode is reduced by the capacitor.

Active matrix display device

An insulated gate field effect transistor is constructed by first forming a non-single crystalline semiconductor layer or island on an insulating surface of a substrate. A gate insulating layer is then formed on the semiconductor layer. A gate electrode is formed on the gate insulating layer. An impurity is added to a portion of the semiconductor layer to form source and drain regions, and the semiconductor layer is irradiated with light through the gate insulating layer. In preferred embodiments, the substrate is maintained at a temperature less than 400° C. and the light have a wavelength of 250-600 nm.

Insulated gate field effect transistor and its manufacturing method

The structure and interfacial reaction in sputtered Mo‐Si multilayers have been studied using cross‐section transmission electron microscopy, electron diffraction, Rutherford backscattering, and low‐angle x‐ray diffraction. Low‐temperature (T<550 °C) annealing was performed in a rapid‐thermal‐annealing furnace and in situ in the microscope. No solid‐state amorphization was observed, in spite of the presence of amorphous alloy interfacial layers in the as‐deposited structure. Instead, the amorphous interlayers crystallize, and growth of the crystalline product, hexagonal‐MoSi2, proceeds. The bilayer period contracts during the reaction, as the disilicide is more dense than its constituents.

Interfacial reactions on annealing molybdenum‐silicon multilayers

The characterization of polycrystalline silicon MOS transistors and its film properties are studied, with special emphasis on the relationship between crystalline defects and carrier transport phenomena An increase in mobility with gate field in polycrystalline silicon MOS transistors and also with doping concentration in polycrystalline silicon films is observed These phenomena are interpreted as space charge scattering effects caused by a high density of dislocations in the films U-shaped drain current vs gate voltage curves are observed both in p-channel and n-channel polycrystalline silicon MOS transistors The anomalous drain current in the accumulation region is interpreted as junction breakdown at the drain edge caused by crystalline imperfections in the films

https://iopscience.iop.org/article/10.1143/JJAP.21.1472/pdf

Characterization of Polycrystalline Silicon MOS Transistors and Its Film Properties. I

PURPOSE:To make the characteristic of a transistor uniform for improvement by applying the light beam or the electron beam to the polycrystalline or amorphous semiconductor layer on the substrate surface, before fabricating a transistor on this CONSTITUTION:A polycrystalline Si layer 3 is provided on a base comprising a semiconductor substrate 1 provided with an insulation layer, and to this, the laser beam is applied from above Then an MOS transistor having a source 4, drain 5, gate oxide-film 6, gate electrode 7, insulation film 8, and electrodes 9-11 is fabricated Since the laser irradiation causes many crystal defects and grain boundaries in the polycrystalline Si to disappear, impurities having been trapped by such defects and grain boundaries are electrically activated, so that a great number of electrons or holes are emitted The mobility is also allowed to rise, so that the electric conductivity rises In addition, the pressure tightness of P-N junction is allowed to rise, so that the leakage current decreases

Preparation of semiconductor device

Both 25-stage n-MOS enhancement driver/enhancement load (E/E) and enhancement driver/depletion load (E/D) ring oscillators with a fan out of one composed of 4-µm channel length transistors have been successfully fabricated in CW electron-beam recrystallized polysilicon/Si 3 N 4 /SiO 2 /

n-Channel MOS ring oscillators fabricated in electron-beam recrystallized silicon-on-insulator

Crystalline Structure Changes of Molybdenum Silicide Films Deposited by Sputtering and by Coevaporation after Isochronal Annealing

An electron beam annealing (EBA) system with high current electron-emitter and oil-free pump evacuated chamber was newly developed. Parameters in grain growth of silicon on insulator (SOI) were analyzed, and large grained-poly-si with dimensions of 20 µm × several millimeters was stably and reproducibly obtained on Si3N4 film. MOSFET's (L=1.5 to 50 µm), inverters, and ring oscillators with well controlled threshold voltages were successfully fabricated in the recrystallized SOI. Back interface conductions were clarified by drain current (ID)-back gate voltage (VBG) measurements. A hysteresis loop was found in the ID-VBG relation, which is considered due to charge injection into Si3N4 layer.

Kenji Shibata

Papers

Characterization of Polycrystalline Silicon MOS Transistors and Its Film Properties. I

Preparation of semiconductor device

n-Channel MOS ring oscillators fabricated in electron-beam recrystallized silicon-on-insulator

Crystalline Structure Changes of Molybdenum Silicide Films Deposited by Sputtering and by Coevaporation after Isochronal Annealing

Growth of Large Grained Silicon on Insulator by Electron Beam Annealing and Performance of MOS Devices