General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations.
We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space.
Our DPGA, a fine-grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite-state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds.
Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20$\times$ the computational density of conventional processors.
Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

Reconfigurable Architectures for General-Purpose Computing

Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits. Some basic compatible analog circuit techniques and their related tradeoffs are then surveyed by means of typical examples. The noisy environment due to cohabitation on the chip with digital circuits is briefly evoked.

The Design of High-Performance Analog Circuits on Digital CMOS Chips

The era of low power microelectronics began with the invention of the transistor in the late 1940's and came of age with the invention of the integrated circuit in the late 1950's. Historically, the most demanding applications of low power microelectronics have been battery operated products such as wrist watches, hearing aids, implantable cardiac pacemakers, pocket calculators, pagers, cellular telephones and prospectively the hand-held multi-media terminal However, in the early 1990's low power microelectronics rapidly evolved from a substantial tributary to the mainstream of microelectronics. The principal reasons for this transformation were the increasing packing density of transistors and increasing clock frequencies of CMOS microchips pushing heat removal and power distribution to the forefront of the problems confronting the advance of microelectronics. The distinctive thesis of this discussion is that future opportunities for low power gigascale integration (GSI) will be governed by a hierarchy of theoretical and practical limits whose levels can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit, and (5) system. >

/pdf/low-power-microelectronics-retrospect-and-prospect-52qjazszpc.pdf

Low power microelectronics: retrospect and prospect

This paper presents a comparison of hot-carrier degradation experiments with simulations of hot electron and hole emission into the oxide. It is shown that both the emission of holes and of electrons are essential to explain the dominant generation of negative charge by a new degradation mechanism. Moreover, a peak of positive-charge generation at a gate voltage close to threshold was found in our experiments which is due to hole trapping. A simple degradation model based on the calculated electron and hole emission is presented which gives a very good description of the observed behavior of degradation effects.

Hot-electron and hole-emission effects in short n-channel MOSFET's

The anomalous leakage current I L in LPCVD polysilicon MOSFET's is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce I L , and indicates when the back-surface leakage component is significant.

Anomalous leakage current in LPCVD PolySilicon MOSFET's

A fast, low-power 32K/spl times/8-bit CMOS static RAM with a high-resistive polyload 4-transistor cell has been developed utilizing a dynamic double word line (DDWL) scheme. This scheme combines an automatic power down circuitry and double word line structure. The DDWL, together with bit line and sense line equilibration, reduces the core area delay time and operating power to about 1/2 and 1/15 that of a conventional device, respectively. A newly developed fault-tolerant circuitry improves fabrication yield without degrading the access time. As for a fabrication process, an advanced 1.2-/spl mu/m p-well CMOS technology is developed to realize the ULSI RAM, integrating 1,600,000 elements on a 6.68/spl times/8.86 mm/SUP 2/ chip. The RAM offers, typically, 46 ns access time, 10 mW operating power and 30 /spl mu/W standby power.

A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line

Charge retention in SAMOS structures at elevated temperatures is effectively described by a thermionic electron emission model from a floating polysilicon gate into the surrounding oxide. Experimental results showed sufficiently good agreement with the theoretical model. The barrier height and collision frequency derived from the experiments are reasonable (1.24 eV and 2.5×104/sec, respectively). Long term data retention in floating gate EPROM's can also be predicted by this model.

https://iopscience.iop.org/article/10.1143/JJAP.21.L111/pdf

A Thermionic Electron Emission Model for Charge Retention in SAMOS Structure

The characterization of polycrystalline silicon MOS transistors and its film properties are studied, with special emphasis on the relationship between crystalline defects and carrier transport phenomena An increase in mobility with gate field in polycrystalline silicon MOS transistors and also with doping concentration in polycrystalline silicon films is observed These phenomena are interpreted as space charge scattering effects caused by a high density of dislocations in the films U-shaped drain current vs gate voltage curves are observed both in p-channel and n-channel polycrystalline silicon MOS transistors The anomalous drain current in the accumulation region is interpreted as junction breakdown at the drain edge caused by crystalline imperfections in the films

https://iopscience.iop.org/article/10.1143/JJAP.21.1472/pdf

Characterization of Polycrystalline Silicon MOS Transistors and Its Film Properties. I

A fully static 8K word by 8 bit CMOS RAM, with a six-transistor CMOS cell structure to achieve an extremely low standby power of less than 50 nW has been developed. A 2 /spl mu/m, double polysilicon CMOS process was utilized to realize a 19/spl times/22 /spl mu/m cell size. Redundance technology with polysilicon laser fuses was also developed for improving fabrication yield with relatively large chip size, i.e. 5.92/spl times/7.49 mm. In addition, for reducing operational power dissipation while maintaining fully static operation from outside on the chip, an internally clocked low-power circuit technology using row address transition detectors was employed, which results in only 15 mW operational power at 1 MHz by cutting off all DC current paths. The RAM offers an 80 ns address access time.

An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-µm CMOS with a new "hot carrier resistant" self-defined polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors, it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n+-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n+-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.

Susumu Kohyama

Papers

A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line

A Thermionic Electron Emission Model for Charge Retention in SAMOS Structure

Characterization of Polycrystalline Silicon MOS Transistors and Its Film Properties. I

An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell

1.0-µm n-well CMOS/bipolar technology

Susumu Kohyama

Papers

A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line

A Thermionic Electron Emission Model for Charge Retention in SAMOS Structure

Characterization of Polycrystalline Silicon MOS Transistors and Its Film Properties. I

An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell

1.0-&#181;m n-well CMOS/bipolar technology

1.0-µm n-well CMOS/bipolar technology