Integration of mm-wave multiple-antenna systems on silicon-based processes enables complex, low-cost systems for high-frequency communication and sensing applications. In this paper, the transmitter and LO-path phase-shifting sections of the first fully integrated 77-GHz phased-array transceiver are presented. The SiGe transceiver utilizes a local LO-path phase-shifting architecture to achieve beam steering and includes four transmit and receive elements, along with the LO frequency generation and distribution circuitry. The local LO-path phase-shifting scheme enables a robust distribution network that scales well with increasing frequency and/or number of elements while providing high-resolution phase shifts. Each element of the heterodyne transmitter generates +12.5 dBm of output power at 77 GHz with a bandwidth of 2.5 GHz leading to a 4-element effective isotropic radiated power (EIRP) of 24.5 dBm. Each on-chip PA has a maximum saturated power of +17.5 dBm at 77 GHz. The phased-array performance is measured using an internal test option and achieves 12-dB peak-to-null ratio with two transmit and receive elements active

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A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Transmitter and Local LO-Path Phase Shifting

This paper presents the design of a 60 GHz phase shifter integrated with a low-noise amplifier (LNA) and power amplifier (PA) in a 65 nm CMOS technology for phased array systems. The 4-bit digitally controlled RF phase shifter is based on programmable weighted combinations of I/Q paths using digitally controlled variable gain amplifiers (VGAs). With the combination of an LNA, a phase shifter and part of a combiner, each receiver path achieves 7.2 dB noise figure, a 360° phase shift range in steps of approximately 22.5°, an average insertion gain of 12 dB at 61 GHz, a 3 dB-bandwidth of 5.5 GHz and dissipates 78 mW. Consisting of a phase shifter and a PA, one transmitter path achieves a maximum output power of higher than +8.3 dBm, a 360° phase shift range in 22.5° steps, an average insertion gain of 7.7 dB at 62 GHz, a 3 dB-bandwidth of 6.5 GHz and dissipates 168 mW.

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A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems

A fully integrated CMOS ultra-wideband 4-channel timed array receiver for high-resolution imaging application is presented. A path-sharing true time delay architecture is implemented to reduce the chip area for integrated circuits. The true time delay resolution is 15 ps and the maximum delay is 225 ps. The receiver provides 11 scan angles with almost 9 degrees of spatial resolution for an antenna spacing of 3 cm. The design bandwidth is from 1 to 15 GHz corresponding to less than 1 cm depth resolution in free space. The chip is implemented in 0.13 mum CMOS with eight metal layers, and the chip size is 3.1 mm by 3.2 mm. Measurement results for the standalone CMOS chip as well as the integrated planar antenna array and the CMOS chip are reported.

An Integrated Ultra-Wideband Timed Array Receiver in 0.13 $\mu{\hbox{m}}$ CMOS Using a Path-Sharing True Time Delay Architecture

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 mm2 and 65 mW. The presented receiver targets 60 GHz communication where beamforming is required.

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

At low-GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors and capacitors (g m -C filters). This paper presents an easily cascadable compact g m -C all-pass filter cell for 1-2.5 GHz. Compared to previous g m -RC and g m -C filter cells, it achieves at least 5x larger frequency range for the same relative delay variation, while keeping gain variation within 1 dB. This paper derives design equations for the transfer function and several non-idealities. Circuit techniques to improve phase linearity and reduce delay variation over frequency, are also proposed. A 160 nm CMOS chip with maximum delay of 550 ps is demonstrated with monotonous delay steps of 13 ps (41 steps) and an RMS delay variation error of less than 10 ps over more than an octave in frequency (1-2.5 GHz). The delay per area is at least 50x more than for earlier chips. The all-pass cells are used to realize a four element timed-array receiver IC. Measurement results of the beam pattern demonstrate the wideband operation capability of the g m -RC time delay cell and timed-array IC-architecture.

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Compact cascadable gm-C all-pass true time delay cell with reduced delay variation over frequency

Ultra-wideband (UWB) beam-forming, a special class of multiple-antenna systems, allows for high azimuth and depth resolutions in ranging and imaging applications. This paper reports a fully integrated UWB beam-former featuring controllable true time delay and power gain. Several system and circuit level parameters and characterization methods influencing the design and testing of UWB beam-formers are discussed. A UWB beam-former prototype for imaging applications has been fabricated with the potential to yield 20 mm of range resolution and a 7deg angular resolution from a four-element array with 10 mm element spacing. The UWB beam-former accomplishes a 4-bit delay variation for a total of 64 ps of achievable group delay with a 4-ps resolution, a 5-dB gain variation in 1-dB steps, and a worst case -3-dB gain bandwidth of 13 GHz. Overall operation is achieved by the integration of a 3-bit tapped delay trombone-type structure with a 4-ps variable delay resolution, a 1-bit, 32-ps fixed delay coplanar-type structure, and a variable-gain distributed amplifier. The prototype chip fabricated in a 0.18 mum BiCMOS SiGe process occupies 1.6 mm2 of silicon area and consumes 87.5 mW from a 2.5-V supply at the maximum gain setting of 10 dB

/pdf/silicon-based-ultra-wideband-beam-forming-2gqifcokdw.pdf

Kenneth Newton

Papers

Silicon-Based Ultra-Wideband Beam-Forming