K
Kenneth S. Stevens
Researcher at University of Utah
Publications - 99
Citations - 1583
Kenneth S. Stevens is an academic researcher from University of Utah. The author has contributed to research in topics: Asynchronous communication & Network on a chip. The author has an hindex of 22, co-authored 99 publications receiving 1549 citations. Previous affiliations of Kenneth S. Stevens include Intel & Schlumberger.
Papers
More filters
Proceedings Article
Relative timing
TL;DR: Relative Timing is introduced as an informal method for aggressive asynchronous design and demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits.
Journal ArticleDOI
The Post Office experience: Designing a large asynchronous chip
TL;DR: The Post Office complexity forced the authors to develop a set of design tools capable of correctly synthesizing transistor circuits from state machine and equation specifications, and capable of verifying the correctness of the resultant circuitry using implementation specific timing assumptions.
Journal ArticleDOI
An asynchronous instruction length decoder
Kenneth S. Stevens,Shai Rotem,Ran Ginosar,Peter A. Beerel,Chris J. Myers,K.Y. Yun,R. Koi,C. Dike,Marly Roncken +8 more
TL;DR: A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits and shows significant advantages - in particular, performance of 2.5-4.5 instructions per nanosecond - with manageable risks using this design technology.
Proceedings ArticleDOI
RAPPID: an asynchronous instruction length decoder
Shai Rotem,Kenneth S. Stevens,Ran Ginosar,Peter A. Beerel,Chris J. Myers,K.Y. Yun,Rakefet Kol,C. Dike,Marly Roncken,B. Agapiev +9 more
TL;DR: Results show significant advantages-in particular, performance of 2.5-4.5 instructions/nS-with manageable risks using this design technology, and potential disadvantages of applying an aggressive asynchronous design methodology to Intel Architecture.
Journal ArticleDOI
Relative timing [asynchronous design]
TL;DR: Relative timing (RT) is introduced as a method for asynchronous design and enables improved performance, area, power, and functional testability of up to a factor of 3/spl times/ in all three cases.