Klaus Dietrich Beyer

TL;DR: In this article, a method for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique is disclosed, which is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material.

TL;DR: In this article, a chemical-mechanical (chem-mech) method for removing SiO protuberances at the surface of a silicon chip, such protuberance including "bird heads", is described.

TL;DR: The void-free pattern of isolation in a semiconductor substrate is described in this article, where a pattern of substantially vertically sided trenches is described, where the base or bottom of the trenches are open to the monocrystalline semiconductor body.

TL;DR: In this article, a wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.

TL;DR: In this paper, a wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers, and the first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface of the substrate, the first substrate has a characteristic thermal expansion coefficient.