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Patent

Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique

TLDR
In this article, a chemical-mechanical (chem-mech) method for removing SiO protuberances at the surface of a silicon chip, such protuberance including "bird heads", is described.
Abstract
A chemical-mechanical (chem-mech) method for removing SiO₂ protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si₃N₄ (29) is deposited onto the wafer surface, which is then chem-mech polished with a SiO₂ water based slurry. The Si₃N₄ acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si₃N₄ layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO₂ protuberances are removed to provide a substantially planar integrated structure.

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Chemical mechanical polishing slurry useful for copper substrates

TL;DR: A chemical mechanical polishing slurry comprising an oxidizing agent, a complexing agent, an abrasive, and an optional surfactant was used to remove copper alloy, titanium, titanium nitride, tantalum and tantalum nitride containing layers from a substrate as discussed by the authors.
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Method of modifying an exposed surface of a semiconductor wafer

TL;DR: In this article, a method of modifying an exposed surface of a semiconductor wafer is described, which includes the steps of contacting the surface with a fixed abrasive article having a three-dimensional textured abrasive surface that includes a plurality of abrasive particles and a binder in the form of a pre-determined pattern.
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TL;DR: In this paper, a method of modifying or refining a surface of a wafer suited for semiconductor fabrication is proposed, where the surface of the wafer is modified by contacting and relatively moving the exposed surface with respect to an abrasive article.
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Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology

TL;DR: In this paper, a chemical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays is described, in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) reflowed below the level of the tip, iv) optionally deposited with another insulating materials, v) optionally, deposited with conductive material layer, and vi) optionally and planarized with a chemical mechanical planarization (CMP) step, to expose the conform
References
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Patent

Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking

TL;DR: The lateral intradevice isolation as discussed by the authors enables the simultaneous formation through a single mask of an active region and a contact region for a different active region both on the same planar surface of a semiconductor substrate.
Patent

Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation

TL;DR: In this paper, a V-shaped lateral dielectric isolation groove divides a semiconductor layer into a plurality of regions, and the oxide layer above the polycrystalline material in the grooves is thicker than the field oxide layer on the semiconductor layers to prevent the creation of retrograde surface profiles.
Patent

Silicon wafer polishing

TL;DR: The polishing of monocrystalline silicon wafers with an aqueous composition of fine sized abrasive particles, a soluble alkali metal base such as a sodium carbonate and an oxidizing agent such as sodium or potassium salt of dichloroisocyanuric acid (e.g., salts of halo-trizenetrione) was studied in this paper.
Patent

Method of manufacturing semiconductor devices having improved alignment marks

TL;DR: In this paper, the alignment mark is produced by a thermal oxidizing operation involved in the manufacturing procedure of the V-groove isolation structure, and the alignment marks consist of a locally thick portion of an oxide layer covering an epitaxial layer in which a V-hole is formed.
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Fabricating semiconductor device utilizing a physical ion etching process

TL;DR: An even surface of an SiO 2 layer on an Si body, whose surface is uneven, is obtained by the steps of forming a photoresist layer of KTFR on the uneven surface of the SiO2 layer so as to have a thickness sufficient cover the unevenness of the surface as mentioned in this paper.
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