There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

We will review some of the major results in random graphs and some of the more challenging open problems. We will cover algorithmic and structural questions. We will touch on newer models, including those related to the WWW.

Random graphs

“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

We have witnessed great interest and a wealth of promise in content-based image retrieval as an emerging technology. While the last decade laid foundation to such promise, it also paved the way for a large number of new techniques and systems, got many new people involved, and triggered stronger association of weakly related fields. In this article, we survey almost 300 key theoretical and empirical contributions in the current decade related to image retrieval and automatic image annotation, and in the process discuss the spawning of related subfields. We also discuss significant challenges involved in the adaptation of existing image retrieval techniques to build systems that can be useful in the real world. In retrospect of what has been achieved so far, we also conjecture what the future may hold for image retrieval research.

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Image retrieval: Ideas, influences, and trends of the new age

Computational geometry

Tile art image generation is one of the non‐photorealistic rendering methods. The generated digital image resembles artistic representation given digital photos and illustrations. The first contribution of this paper is to propose a tile image generation based on the greedy approach. The greedy approach is based on the characteristic of the human visual system to optimize generated images. In addition, to shorten the computation time, we show the parallel algorithm and its GPU acceleration technique. We have implemented it on NVIDIA Tesla V100 GPU. The experimental result shows that the GPU implementation attains a speed‐up factor of 318 and 16.19 over the sequential CPU implementation and the parallel multi‐core CPU implementation with 160 threads, respectively. The second contribution of this paper is to propose an approximation method using machine learning with deep neural networks. After learning the network with the tile art images generated by the greedy approach as training dataset, it can generate tile art images that well‐reproduce the original images with tile patterns. Moreover, we show an additional machine learning technique by repeating the forwarding computation for the generated tile art image as an input image. As a result, using this technique, we can generate a tile art images with clear shape of tiles.

Tile art image generation using parallel greedy algorithm on the GPU and its approximation with machine learning

The main contribution of this paper is to show efficient implementations of the convolution-pooling in the GPU, in which the pooling follows the multiple convolution. Since the multiple convolution and the pooling operations are performed alternately in earlier stages of many Convolutional Neural Networks (CNNs), it is very important to accelerate the convolution-pooling. Our new GPU implementation uses two techniques, (1) convolution interchange with direct sum, and (2) conversion to matrix multiplication. By these techniques, the computational and memory access cost are reduced. Further the convolution interchange is converted to matrix multiplication, which can be computed by cuBLAS very efficiently. Experimental results using Telsa V100 GPU show that our new GPU implementation compatible with cuDNN for the convolution-pooling is at least 1.34 times faster than the multiple convolution and then the pooling by cuDNN, the most popular library of primitives to implement the CNNs in the GPU.

Efficient cuDNN-Compatible Convolution-Pooling on the GPU

The bulk execution of a sequential algorithm is to execute it for many different inputs in turn or at the same time. A sequential algorithm is oblivious if the address accessed at each time unit is independent of the input. It is known that the bulk execution of an oblivious sequential algorithm can be implemented to run on a GPU very efficiently. The main purpose of our work is to implement the bulk execution of a Euclidean algorithm computing the GCD (Greatest Common Divisor) of two large numbers in a GPU. We first present a new efficient Euclidean algorithm that we call the Approximate Euclidean algorithm. The idea of the Approximate Euclidean algorithm is to compute an approximation of quotient by just one 64-bit division and to use it for reducing the number of iterations of the Euclidean algorithm. Unfortunately, the Approximate Euclidean algorithm is not oblivious. To show that the bulk execution of the Approximate Euclidean algorithm can be implemented efficiently in the GPU, we introduce a semi-oblivious sequential algorithms, which is almost oblivious. We show that the Approximate Euclidean algorithm can be implemented as a semi-oblivious algorithm. The experimental results show that our parallel implementation of the Approximate Euclidean algorithm for 1024- bit integers running on GeForce GTX Titan X GPU is 90 times faster than the Intel Xeon CPU implementation.Â

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Bulk execution of Euclidean algorithms on the CUDA-enabled GPU

Randomized time-and energy-optical routing in single-hop, single-channel Radio Networks

Field Programmable Gate Arrays (FPGAs) are a dominant implementation medium for digital circuits which are used to embed a circuit designed by users instantly FPGAs can be used for implementing parallel and hardware algorithms Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs) Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations The main contribution of this paper is to provide one of the potent approaches to resolve this problem We assume that a circuit using asynchronous ROMs designed by a non-expert or quickly designed by an expert is given Our goal is to convert the circuit with asynchronous ROMs into an equivalent circuit with synchronous ones The resulting circuit with synchronous ROMs can be embedded into FPGAs

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Koji Nakano

Papers

Tile art image generation using parallel greedy algorithm on the GPU and its approximation with machine learning

Efficient cuDNN-Compatible Convolution-Pooling on the GPU

Bulk execution of Euclidean algorithms on the CUDA-enabled GPU

Randomized time-and energy-optical routing in single-hop, single-channel Radio Networks

An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles