There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

We will review some of the major results in random graphs and some of the more challenging open problems. We will cover algorithmic and structural questions. We will touch on newer models, including those related to the WWW.

Random graphs

“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

We have witnessed great interest and a wealth of promise in content-based image retrieval as an emerging technology. While the last decade laid foundation to such promise, it also paved the way for a large number of new techniques and systems, got many new people involved, and triggered stronger association of weakly related fields. In this article, we survey almost 300 key theoretical and empirical contributions in the current decade related to image retrieval and automatic image annotation, and in the process discuss the spawning of related subfields. We also discuss significant challenges involved in the adaptation of existing image retrieval techniques to build systems that can be useful in the real world. In retrospect of what has been achieved so far, we also conjecture what the future may hold for image retrieval research.

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Image retrieval: Ideas, influences, and trends of the new age

Computational geometry

This paper aims at establishing a method for designing high-performance network topologies to bridge a gap between theoretical and practical studies. To this end, we present a novel graph called a host-switch graph, which consists of host vertices and switch vertices with maximum degree 1 and $r$ , respectively. This graph represents a network topology of a practical parallel/distributed computer system with host computers connected by $r$ -port switches. We discuss important metrics for designing high-performance interconnection networks: the host-to-host average shortest path length (h-ASPL) and the bisection width (BiW). In particular, we explore a method for constructing host-switch graphs with low h-ASPL and high BiW that connect the fixed number of hosts via any number of $r$ -port switches. We demonstrate that the number of switches that provides the minimum h-ASPL can mathematically be approximated, and the minimum number of switches that provides a certain BiW can experimentally be approximated. On the basis of the approximations, we propose a randomized algorithm for searching host-switch graphs. We then apply the graphs to interconnection networks and compare them with typical network topologies. As compared with the torus, the dragonfly, and the fat-tree, our networks attain higher performance and smaller power and costs.

Designing High-Performance Interconnection Networks with Host-Switch Graphs

The broadcast communication model (BCM, for short) is a distributed system with no central arbiter populated by p stations denoted by S(1),S(2),...,S(p) that communicate by transmitting messages on a communication channel. The stations are assumed to have the computing power of a laptop computer and to be synchronous, in particular, they all run the same program, albeit on different data. We assume that a station is expending power while transmitting or receiving messages. As it turns out, one of the most effective energy-saving strategies is to mandate individual stations to power their transceiver off (i.e., go to sleep) whenever they are not transmitting or receiving messages. Suppose that the p stations of the BCM store collectively n items such that station S(i), (1 /spl les/ i /spl les/ p), stores s/sub i/ items. Each of the items has a unique destination which is the identity of the station to which the item must be routed. The goal is to route all the items to their destinations, while expending as little energy as possible. Since, in the worst case, each item must be transmitted at least once, every routing protocol must take at least n time slots to terminate. Furthermore, station S(i), (1 /spl les/ i /spl les/ p), must be awake for at least s/sub i/ + d/sub i/ time slots, where d/sub i/ denotes the number of items destined for S(i). Since, in the BCM, every station is within transmission range from every other station, the design of energy-efficient protocols is highly nontrivial. An additional complication stems from the inherent asymmetry of the routing problem: no destination knows the identity of the sender, precluding a priori arrangements between senders and receivers. The main contribution of this work is to present an energy-efficient routing protocol for the single-channel, p-station BCM. We show that for every f /spl ges/ 1, the task of routing n items in this model can be completed with probability exceeding 1 - 1/f, in n + O(q + ln f) time slots and that no station S(i), (1 /spl les/ i /spl les/ p), has to be awake for more than s/sub i/ + d/sub i/ + O(q/sub i/ + r/sub i/ log p + log f) time slots, where q/sub i/ is the number of stations that have items destined for S(i), q = q/sub 1/ + q/sub 2/ +/spl middot//spl middot//spl middot/+ q/sub p/, and r/sub i/ is the number of stations for which S(i) has items. Since q/sub i/ /spl les/ d/sub i/, r/sub i/ /spl les/ s/sub i/ and q /spl les/ n, our protocol is close to optimal both in terms of overall completion time and energy efficiency.

Energy-efficient routing in the broadcast communication model

The Discrete Memory Machine (DMM) and the Unified Memory Machine (UMM) are theoretical parallel computing models that capture the essence of the shared memory and the global memory of GPUs. It was assumed that warps (i.e. groups of threads) on the DMM and the UMM work synchronously in the round-robin manner. However, warps work asynchronously in the actual GPUs, in the sense that warps may be randomly (or arbitrarily) dispatched for execution. The first contribution of this paper is to introduce an asynchronous version of the DMM and the UMM, in which warps are arbitrarily dispatched. Instead, we assume that threads can execute the ``sync threads'' instruction for barrier synchronization. Since the barrier synchronization operation is costly, we should evaluate and minimize the number of barrier synchronization operations performed by parallel algorithms. The second contribution of this paper is to show a parallel algorithm to compute the sum of \boldmath$n$ numbers in optimal computing time and few barrier synchronization steps. Our parallel algorithm computes the sum of \boldmath$n$ numbers in \boldmath$O({n\over w}+l\log n)$ time units and \boldmath$O(\log{l\over w}+\log\log w)$ barrier synchronization steps using \boldmath$wl$ threads both on the asynchronous DMM and on the asynchronous UMM with width \boldmath$w$ and latency \boldmath$l$. We also prove that the computing time is optimal because it matches the theoretical lower bound. Quite surprisingly, the number of barrier synchronization steps and the number of threads are independent of \boldmath$n$. Even if the input size \boldmath$n$ is quite large, our parallel algorithm computes the sum in optimal time units and a fixed number of sync threads using a fixed number of threads.

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Asynchronous Memory Machine Models with Barrier Synchronization

A radio network is a distributed system with no central shared resource, consisting of n stations each equipped with a radio transceiver. One of the most important parameters to evaluate protocols in the radio networks is the number of awake time slots in which each individual station sends/receives a data packet. We are interested in devising energy-efficient initialization protocols in the single-hop radio network (RN, for short) that assign unique IDs in the range [1, n] to the n stations using few awake time slots. It is known that the RN can be initialized in O(log log n) awake time slots, with high probability, if every station knows the number n of stations in the RN. Also, it has been shown that the RN can be initialized in O(log n) awake time slots even if no station knows n. However, it has been open whether the initialization can be performed in O(log log n) awake time slots when no station knows n.Our main contribution is to provide the breakthrough: we show that even if no station knows n, the RN can be initialized by our protocol that terminates, with high probability, in O(n) time slots with no station being awake for more than O(log log n) time slots. We then go on to design an initialization protocol for the k-channel RN that terminates, with high probability, in O(n/k+(log n)2) time slots with no station being awake for more than O(log log n) time slots.

Doubly-logarithmic energy-efficient initialization protocols for single-hop radio networks

The Discrete Memory Machine (DMM) is a theoretical parallel computing model that captures the essence of memory access of the streaming multiprocessor on CUDA-enabled GPUs. The DMM has w memory banks that constitute a shared memory, and w threads in a warp try to access them at the same time. However, memory access requests destined for the same memory bank are processed sequentially. Hence, it is very important for developing efficient algorithms to reduce the memory access congestion, the maximum number of memory access requests destined for the same bank. The memory access congestion takes value between 1 and w. The main contribution of this paper is to present a novel algorithmic technique called the random address shift that reduces the memory access congestion. We show that the memory access congestion is expected O(log w/log log w) for any memory access requests including malicious ones by a warp of w threads. The simulation results show that the expected congestion for w=32 threads is only 3.436. Since the malicious memory access requests destined for the same bank take congestion 32, our random address shift technique substantially reduces the memory access congestion. We have applied the random address shift technique to matrix transpose algorithms. The experimental results on GeForce GTX Titan show that the random address shift technique is practical and can accelerate the straightforward matrix transpose algorithms by a factor of 5.

Koji Nakano

Papers

Designing High-Performance Interconnection Networks with Host-Switch Graphs

Energy-efficient routing in the broadcast communication model

Asynchronous Memory Machine Models with Barrier Synchronization

Doubly-logarithmic energy-efficient initialization protocols for single-hop radio networks

The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine