There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

We will review some of the major results in random graphs and some of the more challenging open problems. We will cover algorithmic and structural questions. We will touch on newer models, including those related to the WWW.

Random graphs

“Unpaired Image-to-Image Translation using Cycle-Consistent Adversarial Networks”の学習報告

We have witnessed great interest and a wealth of promise in content-based image retrieval as an emerging technology. While the last decade laid foundation to such promise, it also paved the way for a large number of new techniques and systems, got many new people involved, and triggered stronger association of weakly related fields. In this article, we survey almost 300 key theoretical and empirical contributions in the current decade related to image retrieval and automatic image annotation, and in the process discuss the spawning of related subfields. We also discuss significant challenges involved in the adaptation of existing image retrieval techniques to build systems that can be useful in the real world. In retrospect of what has been achieved so far, we also conjecture what the future may hold for image retrieval research.

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Image retrieval: Ideas, influences, and trends of the new age

Computational geometry

An Efficient GPU Implementation of CKY Parsing Using the Bitwise Parallel Bulk Computation Technique

An ASCII art is a matrix of ASCII code characters that reproduces an original grey-scale image. A JIS art is an ASCII art that uses JIS Kanji code characters instead of ASCII code characters. They are commonly used to represent pseudo grey-scale images in text -based messages. Since automatic generation of high quality ASCII/JIS art images is very hard, they are usually produced by hand. The main contribution of this paper is to propose a new technique to generate an ASCII/JIS art that reproduces the original tone and the details of an input grey-scale image. Our new technique is inspired by the local exhaustive search LES to optimise binary images for printing based on the characteristic of the human visual system. Although it can generate high quality ASCII/JIS art images, a lot of computing time is necessary for the LES. Hence, we have implemented our new technique in a graphics processing unit GPU to accelerate the computation. The experimental results show that the GPU implementation can achieve a speedup factor up to 89.56 over the conventional CPU implementation.

A character art generator using the local exhaustive search, with GPU acceleration

Some applications such as RSA encryption/decryption needs integer arithmetic operations with many bits However, such operations cannot be performed directly by conventional CPUs, because their instruction supports integers with fixed bits, say, 64 bits Since the CPUs need to repeat arithmetic operations to numbers with fixed bits, they have considerably overhead to execute applications involving integer arithmetic with many bits On the other hand, we can implement hardware algorithms for such applications in the FPGAs for further acceleration However, the implementation of hardware algorithm is usually very complicated and debugging of hardware is too hard The main contribution of this paper is to present an intermediate approach of software and hardware using FPGAs More specifically, we present a processor based on FDFM (Few DSP slices and Few Memory blocks) approach that supports arithmetic operations with flexibly many bits, and implement it in the FPGA Arithmetic instructions of our processor architecture include addition, subtraction, and multiplication for numbers with variable size longer than 64 bits To show the potentiality of our processor, we have implemented 2048-bit RSA encryption/decryption by software written by machine instructions The resulting processor uses only one DSP48E1 slices and four Block RAMs (BRAMs), and RSA encryption software on it runs in 63565ms It has been shown that the direct hardware implementation of RSA encryption runs in 27726ms Although our intermediate approach is slower, it has several advantages Since the algorithm is written by software, the development and the debugging are easy Also, it is more flexible and scalable

A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs

Several important tasks, including matrix computation, signal processing, sorting, dynamic programming, encryption, and decryption, can be performed by oblivious sequential algorithms. A sequential algorithm is oblivious if an address accessed at each time does not depend on the input data. A bulk execution of a sequential algorithm is to execute it for many independent inputs in turn or in parallel. A number of works have been devoted to design and implement parallel algorithms for a single input. However, none of these works evaluated the bulk execution performance of these algorithms. The first contribution of this paper is to present a time‐optimal implementation for bulk execution of an oblivious sequential algorithm. Our second contribution is to develop a tool, named C2CU, which automatically generates a CUDA C program for a bulk execution of an oblivious sequential algorithm. The C2CU has been used to generate CUDA C programs for the bulk execution of the bitonic sorting, Floyd‐Warshall, and Montgomery modulo multiplication algorithms. Compared to a sequential implementation on a single CPU, the generated CUDA C programs for the above algorithms run, respectively, 199, 54, and 78 times faster.

C2CU: a CUDA C program generator for bulk execution of a sequential algorithm

The main contribution of this paper is to present an efficient multicore CPU implementation of convolution-pooling computation in convolutional neural networks (CNNs). Since the convolution and pooling operations are performed several times in most CNNs, we propose a method to accelerate the operations. In our proposed multicore CPU implementation, we use convolution interchange to reduce the computational cost. Also, we implement convolution-pooling computation efficiently using DNNL that is an open source library for accelerating deep learning frameworks. The experimental results using Intel Corei9-7980XE CPU show that our proposed CPU implementation for the convolution-pooling is 1.42 to 2.82 times faster than the multiple convolution and then pooling by DNNL. Further, we incorporate the proposed implementation into TensorFlow to perform them as a TensorFloW operation. The incorporated implementation for the convolution-pooling is 1.18 to 2.42 times faster than straightforward implementation by primitives in TensorFlow.

Koji Nakano

Papers

An Efficient GPU Implementation of CKY Parsing Using the Bitwise Parallel Bulk Computation Technique

A character art generator using the local exhaustive search, with GPU acceleration

A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs

C2CU: a CUDA C program generator for bulk execution of a sequential algorithm

An Efficient Multicore CPU Implementation for Convolution-Pooling Computation in CNNs.