There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

The celebrated electronic properties of graphene(1,2) have opened the way for materials just one atom thick(3) to be used in the post-silicon electronic era(4). An important milestone was the creation of heterostructures based on graphene and other two-dimensional crystals, which can be assembled into three-dimensional stacks with atomic layer precision(5-7). Such layered structures have already demonstrated a range of fascinating physical phenomena(8-71), and have also been used in demonstrating a prototype field-effect tunnelling transistor(12), which is regarded to be a candidate for post-CMOS (complementary metal-oxide semiconductor) technology. The range of possible materials that could be incorporated into such stacks is very large. Indeed, there are many other materials with layers linked by weak van der Waals forces that can be exfoliated(3,13) and combined together to create novel highly tailored heterostructures. Here, we describe a new generation of field-effect vertical tunnelling transistors where two-dimensional tungsten disulphide serves as an atomically thin barrier between two layers of either mechanically exfoliated or chemical vapour deposition-grown graphene. The combination of tunnelling (under the barrier) and thermionic (over the barrier) transport allows for unprecedented current modulation exceeding 1 x 10(6) at room temperature and very high ON current. These devices can also operate on transparent and flexible substrates.

Vertical field-effect transistor based on graphene?WS2 heterostructures for flexible and transparent electronics

We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

/pdf/low-voltage-tunnel-transistors-for-beyond-cmos-logic-3w5c8knrc5.pdf

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

In this paper, we look into the scaling issues of a vertical tunnel field-effect transistor (FET). The device, a gated p-i-n diode based on silicon, showed gate-controlled band-to-band tunneling from the heavily doped source to the intrinsic channel. An exponentially increasing input characteristics, perfect saturation in the output characteristics, and off-currents of the order of 1 fA//spl mu/m for sub-100-nm channel lengths were observed. Further, with a /spl delta/p/sup +/ SiGe layer at the p-source end, improvements in the device performance in terms of on-current, threshold voltage and subthreshold swing were shown, albeit trading off the off-currents which increase with Ge content x. We show here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to tunnel FET scaling. Further, with gate workfunction engineering, the tunnel FET can be tuned to achieve a high on-current as well as very low off-currents. Due to the perfect saturation in the output characteristics, the device looks good for sub-100-nm low-power analog devices.

Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering

The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.

Vertical tunnel field-effect transistor

The metal–oxide–semiconductor (MOS)-based vertical tunnel field effect transistor (FET) on silicon has been proposed earlier and which showed gate-controlled band-to-band tunneling from the valence band in the heavily doped δp+ layer at source to the conduction band in the inversion channel. In this work, using 2D computer simulation, we further investigate the device performance enhancement with SiGe in the δp+ layer. On-current as well as threshold voltage are seen to improve considerably and meet the roadmap technology requirements. We also show that unlike the conventional MOSFET, the subthreshold swing of the vertical tunnel FET is not limited to the theoretical value of 60 mV/dec at room temperature.

https://iopscience.iop.org/article/10.1143/JJAP.43.4073/pdf

Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer

Using two-dimensional device simulations, the electrical parameters of gated tunnel field-effect transistor (FET) are optimized with a SiGe delta doped layer in the source region. In order to prove the validity of the simulation models we compare simulation results with the experimentally realized tunnel FET on silicon and show that it gives a good match. It is shown that the incorporation of pseudomorphic strained-Si/sub 1-x/Ge/sub x/ layers leads to a significant performance increase. Furthermore, it becomes evident that the improvements are not a direct consequence of bandgap lowering but rather an indirect consequence of tunnel barrier width lowering. This leads to an asymmetry in the n- and the p-channel performance.

A simulation approach to optimize the electrical parameters of a vertical tunnel FET

Experimental results of p-channel silicon vertical tunnel field-effect transistors down to sub-50 nm channel length are shown. As predicted by two-dimensional simulations, we show that the device on-current is nearly independent of channel length scaling. As the drain current is determined by electrons tunneling from the valence band to the conduction band, we show that mobility does not play any role in determining the device characteristics. Low temperature measurements reveal weak positive temperature coefficient in the transfer characteristics due to the dependence of bandgap on temperature. However, as expected for the silicon devices, low on-current is observed. Thus, we propose a lateral tunnel FET on SiGe-on-insulator with high on-currents and symmetric performance in n-channel as well as p-channel operating modes.

https://iopscience.iop.org/article/10.1143/JJAP.45.3106/pdf

Krishna Kumar Bhuwalka

Papers

Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering

Vertical tunnel field-effect transistor

Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer

A simulation approach to optimize the electrical parameters of a vertical tunnel FET

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths