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Ignaz Eisele
Researcher at Bundeswehr University Munich
Publications - 222
Citations - 4429
Ignaz Eisele is an academic researcher from Bundeswehr University Munich. The author has contributed to research in topics: Silicon & Field-effect transistor. The author has an hindex of 32, co-authored 219 publications receiving 4183 citations. Previous affiliations of Ignaz Eisele include Infineon Technologies & Siemens.
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Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering
TL;DR: It is shown here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to Tunnel FET scaling.
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Cobalt oxide based gas sensors on silicon substrate for operation at low temperatures
Jürgen Wöllenstein,M. Burgmair,G. Plescher,T. Sulima,J. Hildenbrand,Harald Böttner,Ignaz Eisele +6 more
TL;DR: In this paper, the gas sensing characteristics and the morphology of cobalt oxide thin films were investigated using X-ray diffraction analysis (XRD), scanning electron microscope (SEM) and Rutherford backscattering (RBS).
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Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer
TL;DR: In this article, the authors further investigated the performance enhancement with SiGe in the δp+ layer and showed that the subthreshold swing of the vertical tunnel FET is not limited to the theoretical value of 60 mV/dec at room temperature.
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Grazing incidence small angle x-ray scattering from free-standing nanostructures
Markus Rauscher,R. Paniago,Hartmut Metzger,Zoltan Kovats,Jan Domke,J. Peisl,H.-D. Pfannes,Jörg Schulze,Ignaz Eisele +8 more
TL;DR: In this paper, the authors developed the theory for grazing incidence small-angle x-ray scattering (GISAXS) from nanometer-sized naked islands on a flat substrate in the framework of the distorted-wave Born approximation (DWBA).
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A simulation approach to optimize the electrical parameters of a vertical tunnel FET
TL;DR: In this article, the electrical parameters of gated tunnel field effect transistor (FET) were optimized with a SiGe delta doped layer in the source region, which leads to an asymmetry in the n-and p-channel performance.