K
Krishna Lal Baishnab
Researcher at National Institute of Technology, Silchar
Publications - 94
Citations - 573
Krishna Lal Baishnab is an academic researcher from National Institute of Technology, Silchar. The author has contributed to research in topics: Amplifier & Computer science. The author has an hindex of 10, co-authored 84 publications receiving 358 citations.
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Journal ArticleDOI
HWPSO: A new hybrid whale-particle swarm optimization algorithm and its application in electronic design optimization problems
Naushad Manzoor Laskar,Koushik Guha,Indronil Chatterjee,Saurav Chanda,Krishna Lal Baishnab,P. K. Paul +5 more
TL;DR: The simulation results indicate that the proposed HWPSO algorithm outperforms many state of the art algorithms by achieving a better optima with a very low standard deviation for most of the benchmark functions used.
Proceedings ArticleDOI
A Review and Research Towards Mobile Cloud Computing
Dipayan Dev,Krishna Lal Baishnab +1 more
TL;DR: This paper will give a review of various challenges in this field and measures to overcome such in the security policies of mobile cloud computing.
Journal ArticleDOI
Design and simulation of fixed–fixed flexure type RF MEMS switch for reconfigurable antenna
K. Srinivasa Rao,P. Ashok Kumar,Koushik Guha,B. V. S. Sailaja,K. V. Vineetha,Krishna Lal Baishnab,K. Girija Sravani,K. Girija Sravani +7 more
TL;DR: In this article, the design and simulation of RF MEMS switch taken on Microstrip patch antenna loaded with the circular type CSRR is presented, where the two switches moves from upstate to down state arranged on the feeding line provided with the CPW.
Journal ArticleDOI
LRBC: a lightweight block cipher design for resource constrained IoT devices
TL;DR: A new lightweight encryption method called LRBC has been proposed in this work for resource constraint IoT devices which can provide data security at the sensing level and ensures high security against various attacks with robustness.
Proceedings ArticleDOI
A novel ROM architecture for reducing bubble and metastability errors in high speed flash ADCs
TL;DR: A novel ROM architecture has been proposed which suppresses metastability, both first and second order bubble errors, and eliminates the need of an error correction circuit in the front end of the ROM thereby reducing power consumption, area requirement and removing the delay associated with the additional stage.