In this article, we investigate the electrical properties of In0.53Ga0.47As gate-all-around (GAA) MOSFETs with different nanowire shapes. InGaAs GAA MOSFETs with trapezoid and triangle nanowire shapes have been fabricated and characterized. Improved output performance was observed as the nanowire top width reduces from 20 to 11 nm. It was found that the electrical characteristics degraded as the nanowire top width was decreased to nearly 0 nm. To explain the carrier transport mechanism in ultralow-scale devices, TCAD simulation has been performed to study the electron density distribution for different nanowire widths and explain the transport mechanism in these ultralow-scale transistor devices.

Electrical Characteristics of In0.53Ga0.47As Gate-All-Around MOSFETs With Different Nanowire Shapes

The influence of different annealing processes including post deposition annealing (PDA) and post metallization annealing (PMA) with various temperatures (250–400 °C) and ambient [N2 and forming gas (FG)] on the electrical characteristics of Pt/Al2O3/In0.53Ga0.47As MOSCAPs are systemically studied. Comparing to samples underwent high PDA temperature, the higher leakage current has been observed for all of samples underwent high PMA temperature. This has resulted in the degradation of capacitance–voltage (C–V) behaviors. In conjunction with the current–voltage (J–V) measurement, depth profiling Auger electron spectroscopy (AES) and high-resolution transmission electron microscopy (HRTEM) analyses evidence that the out-diffusion of metal into oxide layer is the main source of leakage current. The noticeable passivation effect on the Al2O3/InGaAs interface has also been confirmed by the samples that underwent PDA process.

Effect of annealing processes on the electrical properties of the atomic layer deposition Al

In this work, we demonstrated considerable enhancement of the transport characteristics of n-type Al2O3/In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors (n-MOSFETs) with the assistance of in situ NH3/N2 remote-plasma (RP) treatment. According to the measurement and simulation results, the RP treated sample shows superior device performances as compared to the control sample without plasma treatment including (a) improved on-current (Ion) from 8.5 mA/mm to 17 mA/mm, (b) improved transconductance (Gm) from 16.05 mS/mm to 28.52 mS/mm, (c) suppressed subthreshold swing from 189 mV/dec to 170 mV/dec, (d) suppressed drain induced barrier lowering from 36 mV/V to 28 mV/V, (e) intensified peak effective mobility (μeff) from 1896 cm2 V−1 s−1 to 2956 cm2 V−1 s−1, and (f) reduced acceptor-type density of interface trap state (Dit,A) to 44%. By using TCAD simulation, device output performance is found to be dramatically impacted by the trap state (especially acceptor-type) at the Al2O3/InGaAs interface.

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Investigation of device transport characteristics enhancement of In0.53Ga0.47As MOSFET through in situ NH3/N2 remote-plasma treatment

In this article, sub-10 nm top width nanowire In0.53Ga0.47As gate-all-around (GAA) MOSFETs with improved subthreshold characteristics and reliability are demonstrated. These devices exhibit a significant improvement in the subthreshold performances with subthreshold swing (SS) of 70 mV/dec, drain induced barrier lowering (DIBL) of 46 mV/V, and off-current (<inline-formula> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ off}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math notation="LaTeX">$1.6 \times 10^{-4} \mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> for InGaAs GAA MOSFETs. Effective control of short channel effects (SCEs) is confirmed by the error bar of statistical variation analysis. Under gate bias stress, a low degradation of SS and threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ th}}$ </tex-math></inline-formula>) shift has been achieved due to N2 RP treatment of the InGaAs GAA MOSFETs. The superior performance can be attributed to the strong electrostatic control and high quality of high-<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula>/InGaAs interface, originating from shrinking nanowire width and RP passivation effects. These results show the developed GAA MOSFET devices have good potential for future low-power high-switching speed CMOS logic applications.

Sub-10 nm Top Width Nanowire InGaAs Gate-All-Around MOSFETs With Improved Subthreshold Characteristics and Device Reliability

In this study, we have presented a source-connected field plate (SCFP) InAs high electron mobility transistor (HEMT) and evaluated its potential for using in high-speed and low-power logic applications. The fabricated device demonstrated good electrical characteristics including low subthreshold swing (SS) of 76 mV/decade, drain induced barrier lowering (DIBL) of 44 mV/V, ION/IOFF ratio of 2.4 × 104, an off-state gate leakage current of less than 5 × 10−6 A/mm and a Gm,max of 1100 mS/mm at VDS = 0.5 V. When increasing the drain-source bias (VDS) to 1.0 V, the Gm,max increased to 1750 mS/mm with a cut-off frequency of 113 GHz. These results revealed that the fabrication of source-connected field plate InAs HEMTs achieved excellent device performance for high-speed and low-power logic applications.

Evaluation of an InAs HEMT with source-connected field plate for high-speed and low-power logic applications

This letter presents a remote NH3/N2 plasma treatment after gate oxide deposition for improving the electrical characteristics and the reliability of In0.53Ga0.47As FinFET. The plasma treatment enhanced drive current ( ${I}_{\textsf {DS}}$ ), transconductance ( ${G}_{m}$ ), subthreshold swing (SS), flicker noise, and positive bias temperature lifetime, suggesting that this plasma treatment significantly improves the quality of the etched In0.53Ga0.47As channel interface. In0.53Ga0.47As FinFETs and gate-all-around FETs were fabricated with the proposed in situ remote-plasma treatment and characterized.

Kun Sheng Yang

Papers

In 0.53 Ga 0.47 As FinFET and GAA-FET With Remote-Plasma Treatment