Communication at millimeter wave (mmWave) frequencies is defining a new era of wireless communication. The mmWave band offers higher bandwidth communication channels versus those presently used in commercial wireless systems. The applications of mmWave are immense: wireless local and personal area networks in the unlicensed band, 5G cellular systems, not to mention vehicular area networks, ad hoc networks, and wearables. Signal processing is critical for enabling the next generation of mmWave communication. Due to the use of large antenna arrays at the transmitter and receiver, combined with radio frequency and mixed signal power constraints, new multiple-input multiple-output (MIMO) communication signal processing techniques are needed. Because of the wide bandwidths, low complexity transceiver algorithms become important. There are opportunities to exploit techniques like compressed sensing for channel estimation and beamforming. This article provides an overview of signal processing challenges in mmWave wireless systems, with an emphasis on those faced by using MIMO communication at higher carrier frequencies.

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

Hybrid analog/digital multiple-input multiple-output architectures were recently proposed as an alternative for fully digital-precoding in millimeter wave wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open-loop compressive channel estimation technique that is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimate, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the tradeoffs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

Hybrid analog/digital MIMO architectures were recently proposed as an alternative for fully-digitalprecoding in millimeter wave (mmWave) wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open loop compressive channel estimation technique which is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimated, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the trade-offs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ( $2\times 2$ ) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) mode with 6-bit phase control and 14-dB gain control. The phase change with gain control is only ±3°, allowing orthogonality between the variable gain amplifier and the phase shifter. The chip has high RX linearity (IP1dB = −22 dBm/channel) and consumes 130 mW in the RX mode and 200 mW in the TX mode at P1dB per channel. Advantages of the scalable all-RF beamforming architecture and circuit design techniques are discussed in detail. 4- and 32-element phased-arrays are demonstrated with detailed data link measurements using a single or eight of the four-channel TRX core chips on a low-cost printed circuit board with microstrip antennas. The 32-element array achieves an effective isotropic radiated power (EIRP) of 43 dBm at P1dB, a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB when the beamformer loss and transceiver NF are taken into account and can scan to ±50° in azimuth and ±25° in elevation with < −12-dB sidelobes and without any phase or amplitude calibration. A wireless link is demonstrated using two 32-element phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s in a single beam using 16-QAM waveforms over all scan angles at a link distance of 300 m.

A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a $2\times 2$ Beamformer Flip-Chip Unit Cell

AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 × 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm2 in the TX integrated circuit (IC) and 4.18 mm2 in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern.

60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process

A phase-delay cold-FET pre-distortion linearizer technique is proposed to improve the gain compensation ability compared with the conventional cold-FET pre-distortion linearizer. The gain expansion analysis of the power amplifier (PA) cascading with a pre-distortion linearizer and the comparison with the conventional linearizer and the proposed phase-delay linearizer are provided in this paper. To demonstrate the feasibility of this concept, a single-ended V-band cascode PA with the 90° phase-delay linearizer and a differential K-band common-source PA with the 180° phase-delay linearizer are developed to verify the characteristics. The V-band PA implemented in 90-nm CMOS process exhibits the output 1-dB compression power (OP1 dB) of 13.7 dBm and the power-added efficiency (PAE) at OP1 dB of 14.3%. The K-band PA implemented in 0.18-μm CMOS process demonstrates 17.5-dBm OP1 dB and 13.6% PAE at OP1 dB.

Phase-Delay Cold-FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers

A K-band low-power, low phase noise modified Colpitts VCO was implemented in 0.13 µm CMOS process. The timed current switches of the conventional Colpitts VCO are replaced by a differential transformer, and thus the supply voltage of the proposed VCO can be reduced. The VCO has −100 and −109.5 dBc/Hz phase noises at 1 MHz offset under 4 and 10 mW dc power consumptions, respectively. The chip size is 570 × 570 µm2.

A K-band CMOS low power modified colpitts VCO using transformer feedback

This paper demonstrates a successive second-order intermodulation feed-forward cancelling path, which can reduce the third-order intermodulation distortion (IMD3) of a 24 GHz cascode power amplifier (PA) effectively. By adopting this technique, the P sat , OP 1dB , and associated PAE are 16.6 dBm, 14.6 dBm, and 12.6%, respectively. The sweet-spot locates at 5 dBm output power with 20 dB IMD3 reduction. The P out with the IMD3 better than −40 dBc is 7.9 dBm which is 3.7 dB improvement compared with the PA with turn-off auxiliary path.

A 24 GHz CMOS power amplifier with successive IM2 feed-forward IMD3 cancellation

Two 60-GHz compact double-balanced gate-pumped mixers using standard bulk 0.13 ?m CMOS process are presented. The homodyne and heterodyne mixers utilize small-size combined hybrids and demonstrated a small chip size of 0.8 × 0.85 and 0.7 × 0.7 mm2, including pads. With 5 dBm LO power, the best measured conversion gains are 1 and 0 dB in the 3 dB bandwidths of 15 GHz from 54 to 69 GHz and 14 GHz from 53 to 67 GHz RF. The LO-to-RF isolations are greater than 45 dB at a low bias of 1.2 V and 12 m A. This is the first demonstration of the double-balanced gate mixer in millimeter wave frequency.

Kun-Yao Kao

Papers

60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process

Phase-Delay Cold-FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers

A K-band CMOS low power modified colpitts VCO using transformer feedback

A 24 GHz CMOS power amplifier with successive IM2 feed-forward IMD3 cancellation

60 GHz Double-Balanced Gate-Pumped Down-Conversion Mixers With a Combined Hybrid on 130 nm CMOS Processes