Communication at millimeter wave (mmWave) frequencies is defining a new era of wireless communication. The mmWave band offers higher bandwidth communication channels versus those presently used in commercial wireless systems. The applications of mmWave are immense: wireless local and personal area networks in the unlicensed band, 5G cellular systems, not to mention vehicular area networks, ad hoc networks, and wearables. Signal processing is critical for enabling the next generation of mmWave communication. Due to the use of large antenna arrays at the transmitter and receiver, combined with radio frequency and mixed signal power constraints, new multiple-input multiple-output (MIMO) communication signal processing techniques are needed. Because of the wide bandwidths, low complexity transceiver algorithms become important. There are opportunities to exploit techniques like compressed sensing for channel estimation and beamforming. This article provides an overview of signal processing challenges in mmWave wireless systems, with an emphasis on those faced by using MIMO communication at higher carrier frequencies.

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

Hybrid analog/digital multiple-input multiple-output architectures were recently proposed as an alternative for fully digital-precoding in millimeter wave wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open-loop compressive channel estimation technique that is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimate, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the tradeoffs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

Hybrid analog/digital MIMO architectures were recently proposed as an alternative for fully-digitalprecoding in millimeter wave (mmWave) wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open loop compressive channel estimation technique which is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimated, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the trade-offs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.

Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 × 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm2 in the TX integrated circuit (IC) and 4.18 mm2 in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern.

60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process

In this paper, the design and analysis of CMOS multicascode configuration with noise reduction topology are proposed. Two low power and miniature low-noise amplifiers (LNAs) were designed and fabricated for demonstration. One with cascode device was designed at V -band in 65-nm process, and the other with triple-cascode structure was fabricated at Q -band in 0.13-? m technology. To minimize the noise figure and maximize the small-signal gain, inductors are designed and placed between transistors of the cascode and triple-cascode configurations. Based on this approach, the Q-band LNA has a gain of 14.3 dB and a noise figure of 3.8 dB at 38 GHz, with a power consumption of 28.8 mW. The V-band LNA presents a gain of 14.4 dB and a noise figure of 4.5 dB at 54.5 GHz, with a power consumption of 10 mW. The chip size of the V- and Q-band LNAs are 0.55 × 0.45 mm2 and 0.42 × 0.6 mm2, including all the testing pads. Compared with the conventional cascode LNAs, the proposed cascode LNA shows better noise figure and lower power consumption whereas the triple-cascode LNA features higher gain performance.

Millimeter-Wave Low Power and Miniature CMOS Multicascode Low-Noise Amplifiers with Noise Reduction Topology

A 60GHz six-port transceiver IC in a standard-bulk 0.13mum CMOS process is reported. This chip is composed of a VCO, a modified reflection-type I/Q modulator, a buffer amplifier, an SPDT switch, an LNA, and a six-port detector. The measured results show 4.5dB conversion gain and 4Gb/s modulation BW with 97.7mW DC power consumption.

A 60GHz Low-Power Six-Port Transceiver for Gigabit Software-Defined Transceiver Applications

This paper describes the design of millimeter-wave wide-band monolithic GaAs passive high electron-mobility transistor (HEMT) switches using the traveling-wave concept. This type of switch combined the off-state shunt transistors and series microstrip lines to form an artificial transmission line with 50-/spl Omega/ characteristic impedance. A 15-80-GHz single-pole double-throw (SPDT) switch in conjunction with quarter-wavelength impedance transformers demonstrates an insertion loss of less than 3.6 dB and an isolation of better than 25 dB. Another type of wide-band switch was designed by using a series HEMT switch to replace the quarter-wavelength transformer, and the operating band can be extended to dc. With this scheme, dc-80-GHz single-pole single-throw (SPST) and dc-60-GHz SPDT switches are also developed with compact chip size. From dc to 80 GHz, the insertion loss and isolation of the SPST switch are better than 3 and 24 dB, respectively. The SPDT switch has an insertion loss of better than 3 dB and an isolation of better than 25 dB from dc to 60 GHz. The analysis of circuit characteristics and design procedures are also included. It is concluded that the device periphery can be selected for the desired bandwidth, while the number of transistors is decided to achieve the isolation.

Kun-You Lin

Papers

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process

Millimeter-Wave Low Power and Miniature CMOS Multicascode Low-Noise Amplifiers with Noise Reduction Topology

A 60GHz Low-Power Six-Port Transceiver for Gigabit Software-Defined Transceiver Applications

Millimeter-wave MMIC passive HEMT switches using traveling-wave concept