Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the “curse of dimensionality,” which makes learning tasks exponentially more difficult as dimension increases. Deep machine learning (DML) mimics the hierarchical presentation of information in the human brain to achieve robust automated feature extraction, reducing the dimension of such data. However, the computational complexity of DML systems limits large-scale implementations in standard digital computers. Custom analog or mixed-mode signal processors have been reported to yield much higher energy efficiency than DSP [1-4], presenting the means of overcoming these limitations. However, the use of volatile digital memory in [1-3] precludes their use in intermittently-powered devices, and the required interfacing and internal A/D/A conversions add power and area overhead. Nonvolatile storage is employed in [4], but the lack of learning capability requires task-specific programming before operation, and precludes online adaptation.

30.10 A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13μm CMOS

In neuromorphic hardware, peripheral circuits and memories based on heterogeneous devices are generally physically separated. Thus, exploration of homogeneous devices for these components is key fo...

2D materials-based homogeneous transistor-memory architecture for neuromorphic hardware.

This work develops a thorough review of bioimpedance systems for healthcare applications. The basis and fundamentals of bioimpedance measurements are described covering issues ranging from the hardware diagrams to the configurations and designs of the electrodes and from the mathematical models that describe the frequency behavior of the bioimpedance to the sources of noise and artifacts. Bioimpedance applications such as body composition assessment, impedance cardiography (ICG), transthoracic impedance pneumography, electrical impedance tomography (EIT), and skin conductance are described and analyzed. A breakdown of recent advances and future challenges of bioimpedance is also performed, addressing topics such as transducers for biosensors and Lab-on-Chip technology, measurements in implantable systems, characterization of new parameters and substances, and novel bioimpedance applications.

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Fundamentals, Recent Advances, and Future Challenges in Bioimpedance Devices for Healthcare Applications

Conducting polymers, such as the p-doped poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), have enabled the development of an array of opto- and bio-electronics devices. However, to make these technologies truly pervasive, stable and easily processable, n-doped conducting polymers are also needed. Despite major efforts, no n-type equivalents to the benchmark PEDOT:PSS exist to date. Here, we report on the development of poly(benzimidazobenzophenanthroline):poly(ethyleneimine) (BBL:PEI) as an ethanol-based n-type conductive ink. BBL:PEI thin films yield an n-type electrical conductivity reaching 8 S cm−1, along with excellent thermal, ambient, and solvent stability. This printable n-type mixed ion-electron conductor has several technological implications for realizing high-performance organic electronic devices, as demonstrated for organic thermoelectric generators with record high power output and n-type organic electrochemical transistors with a unique depletion mode of operation. BBL:PEI inks hold promise for the development of next-generation bioelectronics and wearable devices, in particular targeting novel functionality, efficiency, and power performance. The development of n-type conductive polymer inks is critical for the development of next-generation opto-electronic devices that rely on efficient hole and electron transport. Here, the authors report an alcohol-based, high performance and stable n-type conductive ink for printed electronics.

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A high-conductivity n-type polymeric ink for printed electronics.

Novel pervasive devices such as smart surveillance cameras and autonomous micro-UAVs could greatly benefit from the availability of a computing device supporting embedded computer vision at a very low power budget. To this end, we propose PULP (Parallel processing Ultra-Low Power platform), an architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability that exploit the capabilities of the STMicroelectronics UTBB FD-SOI 28nm technology. We show that PULP performance can be scaled over a 1x-354x range, with a peak theoretical energy efficiency of 211 GOPS/W. We present performance results for several demanding kernels from the image processing and vision domain, with post-layout power modeling: a motion detection application that can run at an efficiency up to 192 GOPS/W (90 % of the theoretical peak); a ConvNet-based detector for smart surveillance that can be switched between 0.7 and 27fps operating modes, scaling energy consumption per frame between 1.2 and 12mJ on a 320 ×240 image; and FAST + Lucas-Kanade optical flow on a 128 ×128 image at the ultra-low energy budget of 14 μJ per frame at 60fps.

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision

An ultra-low power true random number generator (TRNG) based on a sub-ranging SAR analog-to-digital converter (ADC) is proposed. The proposed TRNG is composed of a coarse-SAR ADC with a low-power adaptive-reset comparator and a low-power dynamic amplifier. The coarse-ADC part is shared with a sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time chaotic circuit but also reduces the overall SAR ADC energy consumption by selectively activating the fine-SAR ADC. Also, the proposed dynamic residue amplifier consumes only 48 nW and the adaptive-reset comparator generates a chaotic map with only 6-nW consumption. The proposed TRNG core occupies 0.0045 mm2 in 0.18- $\mu \text{m}$ CMOS technology and consumes 82 nW at 270-kbps throughput with 0.6-V supply. It successfully passes all of National Institute of Standards and Technology (NIST) tests, and it achieves the state-of-the-art figure-of-merit of 0.3 pJ/bit.

A 82-nW Chaotic Map True Random Number Generator Based on a Sub-Ranging SAR ADC

The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. Quantum-mechanical band-to-band tunnelling can be used to create an energy-efficient ternary logic technology that can be fabricated on the wafer scale using complementary metal–oxide–semiconductor (CMOS) processes.

Tunnelling-based ternary metal–oxide–semiconductor technology

A low-energy 40/160 MHz dual-band full duplex body channel communication (BCC) transceiver and a 13.56 MHz R-C oscillator-based super-regenerative transceiver are integrated in 65 nm CMOS mixed mode process for both entertainment and healthcare applications. The on-chip R-C duplexer uses notch filters for full duplex communication with 40 Mb/s data rate and combined dual-band operation shows 80 Mb/s data rate with half duplex communication. 40 MHz sine wave and 160 MHz rectangular wave are adopted for modulation in the dual-band transmitter with 30 dB SNR improvement, and shared-loop BPSK receiver reduces the power consumption by 25%. The proposed super-regenerative transceiver including an OOK transmitter and an R-C oscillator-based receiver achieves ${>}60\,\text{dB}$ interference rejection with 100 kb/s data rate and $42.5\,\upmu\text{W}$ power consumption under the 0.8 V supply.

A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a $42.5\;\upmu\text{W}$ 100 kb/s Super-Regenerative Transceiver for Body Channel Communication

A wearable electrical impedance tomography (EIT) system is proposed for the portable real-time 3-D lung ventilation monitoring. It consists of two types of SoCs, active electrode (AE)-SoC and Hub-SoC, mounted on wearable belts. The 48-channel AE-SoCs are integrated on flexible printed circuit board belt, and Hub-SoC is integrated in the hub module which performs data gathering and wireless communication between an external imaging device. To get high accuracy under the variation of conductivity, the dual-mode current stimulator provides the optimal frequency for time difference-EIT and frequency difference-EIT with simultaneous 4 k–128 kHz impedance sensing. A wide dynamic range instruments amplifier is proposed to provide 94 dB of wide dynamic range impedance sensing. In addition, the 48-channel AE system with the dedicated communication and calibration is implemented to achieve 1.4- $\text{m}\Omega $ sensitivity of impedance difference in the in vivo environment. The AE-/Hub-SoCs occupy 3.2 and 1.3 mm2 in 65-nm CMOS technology and consume $124~\mu \text{W}$ and 1.1 mW with 1.2 V supply, respectively. As a result, EIT images are reconstructed with 90% of accuracy, and up to 10 frames/s real-time 3-D lung images are successfully displayed.

A 1.4-m $\Omega$ -Sensitivity 94-dB Dynamic-Range Electrical Impedance Tomography SoC and 48-Channel Hub-SoC for 3-D Lung Ventilation Monitoring System

Object recognition processors have been reported for the applications of autonomic vehicle navigation, smart surveillance and unmanned air vehicles (UAVs) [1-3]. Most of the processors adopt a single classifier rather than multiple classifiers even though multi-classifier systems (MCSs) offer more accurate recognition with higher robustness [4]. In addition, MCSs can incorporate the human vision system (HVS) recognition architecture to reduce computational requirements and enhance recognition accuracy. For example, HMAX models the exact hierarchical architecture of the HVS for improved recognition accuracy [5]. Compared with SIFT, known to have the best recognition accuracy based on local features extracted from the object [6], HMAX can recognize an object based on global features by template matching and a maximum-pooling operation without feature segmentation. In this paper we present a multi-classifier many-core processor combining the HMAX and SIFT approaches on a single chip. Through the combined approach, the system can: 1) pay attention to the target object directly with global context consideration, including complicated background or camouflaging obstacles, 2) utilize the super-resolution algorithm to recognize highly blurred or small size objects, and 3) recognize more than 200 objects in real-time by context-aware feature matching.

Kyuho Jason Lee

Papers

A 82-nW Chaotic Map True Random Number Generator Based on a Sub-Ranging SAR ADC

Tunnelling-based ternary metal–oxide–semiconductor technology

A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a $42.5\;\upmu\text{W}$ 100 kb/s Super-Regenerative Transceiver for Body Channel Communication

A 1.4-m $\Omega$ -Sensitivity 94-dB Dynamic-Range Electrical Impedance Tomography SoC and 48-Channel Hub-SoC for 3-D Lung Ventilation Monitoring System

A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition