Non-volatile storage memory is widely considered to be one of the most promising candidates to replace dynamic random access memory and even static random access memory It has recently received particular attention because of its great potential for brain-like neuromorphic applications Phase-change materials, also known as Chalcogenide alloys, exhibit several especially advantageous traits for non-volatile applications These include scalability, fast switching speeds, low switching energy and outstanding thermal stability As a result, most research to date has sought to identify electrical applications for phase-change materials in relation to phase-change random access memory, phase-change memristors and phase-change neuro networks, while overlooking their potential for non-volatile photonic applications To address this issue, we provide a comprehensive review that examines the remarkable physical properties of phase-change materials for photonic applications, together with emerging phase-change photonic devices The review begins by presenting the atomic structure and physical properties of phase-change materials, followed by an elaboration of the issues that phase-change materials are currently facing and the strategies being developed to overcome them The current state-of-the-art and technical challenges confronting phase-change materials in relation to non-volatile photonic applications, such as phase-change photonic memory, phase-change photonic neuro-networks, phase-change metasurfaces and phase-change color displays are then considered The review concludes by discussing the outlook for successfully implementing phase-change materials in emerging photonic domains

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Overview of Phase-Change Materials Based Photonic Devices

In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.

Architecture and Process Integration Overview of 3D NAND Flash Technologies

In order to resolve the issue of tremendous energy consumption in conventional artificial intelligence, hardware-based neuromorphic system is being actively studied. Although various synaptic devices for the system have been proposed, they have shown limits in terms of endurance, reliability, energy efficiency, and Si processing compatibility. In this work, we design a synaptic transistor with short-term and long-term plasticity, high density, high reliability and energy efficiency, and Si processing compatibility. The synaptic characteristics of the device are closely examined and validated through technology computer-aided design (TCAD) device simulation. Consequently, full synaptic functions with high energy efficiency have been realized.

https://www.mdpi.com/2079-9292/8/10/1102/pdf

A Silicon-Compatible Synaptic Transistor Capable of Multiple Synaptic Weights toward Energy-Efficient Neuromorphic Systems

In this work, nanoscale wedge-structured silicon nitride (SiN x )-based resistive-switching random-access memory with data non-volatility and conductance graduality has been designed, fabricated, and characterized for its application in the hardware neuromorphic system. The process integration with full Si-processing-compatibility for constructing the unique wedge structure by which the electrostatic effects in the synaptic device operations are maximized is demonstrated. The learning behaviors of the fabricated synaptic devices are shown. In the end, vector-matrix multiplication is experimentally verified in the array level for application in more energy-efficient hardware-driven neuromorphic systems.

Nanoscale wedge resistive-switching synaptic device and experimental verification of vector-matrix multiplication for hardware neuromorphic application

In this work, a novel synaptic transistor has been proposed and analyzed through technology computer-aided design (TCAD) simulation. The proposed device has merits of full-Si processing compatibility, short- and long-term plasticity, high energy efficiency, and linear and symmetric conductance adjustability. The proposed device consists of a quantum-well structure and a charge-trap unit for realizing both short- and long-term memories, respectively. The quantum-well charge-trap synaptic transistor (QW CTS) employs two independent gates to separate inference and weight adjustment operation. An optimally designed and validated QW CTS has demonstrated a highly linear and symmetric weight tunability, with an ultra-low energy consumption of ~1.5 fJ per synaptic event. The QW CTS can be a core element in the hardware-driven Si neuromorphic system.

/pdf/a-quantum-well-charge-trap-synaptic-transistor-with-highly-147nm8zdm2.pdf

A Quantum-Well Charge-Trap Synaptic Transistor With Highly Linear Weight Tunability

Investigation on Phase-change Synapse Devices for More Gradual Switching

Ever-growing applications, such as 5G communication, deep learning, advanced driver-assistance systems (ADAS), and extended reality (XR), have fueled demand for increased computing power and per-pin interface bandwidth. Recently, four-level pulse-amplitude modulation (PAM4) has been adopted as a solution [1-3]: the throughput is doubled without increasing the baud (Nyquist) rate. Compared to a conventional non-return-to-zero (NRZ) signaling, PAM4 requires more design effort: varying from the precise design of I/O circuits to the off-chip characterization. This is in part due to SNR degradation and an increased switching jitter (SWJ). For a $1^{\text{st}}$-order low-pass filter with a Nyquist-frequency cutoff, SWJ is 35% for the middle eye and 51.2% for the top and bottom eyes [4]. Maximum-transition-avoidance (MTA) encoding [3] can be used to reduce SWJ, but at the cost of additional encoder/decoder hardware and an auxiliary channel to compensate for data loss.

A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization

A 32Gb/s/lane NRZ wireline transceiver for the cellular mobile interface has been implemented. The maximum data bandwidth is 64Gb/s downlink and 32Gb/s uplink which meets the bandwidth requirement of the next FR2 standard. The master-slave LDO regulation is used to supply the stable power at each transmitter and receiver that operates independently. The dedicated clock correction and the channel adaptation have been performed to satisfy the time margin of 0.28UI at bit error rate (BER) of 10−12.

A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET

Kyunghwan Min

Papers

Investigation on Phase-change Synapse Devices for More Gradual Switching

A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization

A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET