A software-defined radio (SDR) receiver with baseband programmable RF bandpass filter (BPF) and complex impedance match is presented. The passive mixer-first architecture used here allows the impedance characteristics of the receiver's baseband circuits to be translated to the RF port of the receiver. Tuning the resistance at the baseband port allows for a real impedance match to the antenna. The addition of "complex feedback" between I and Q paths allows for matching to the imaginary component of the antenna impedance. By implementing both real and imaginary components with resistors in feedback around low noise baseband amplifiers, noise figure is also kept low. Tunable sampling capacitors on the baseband side of the passive mixer translate to tunable-Q filters on the RF port which allow for very good out-of-band linearity. Furthermore, the concept of in-band and out-of-band must be redefined as the impedance match and BPF center frequency move with the LO frequency, such that matching and filtering track the receive frequency. Additionally, 8-phase mixing is shown to provide significant benefits such as impedance matching range, rejection of blockers at LO harmonics, and lower noise figure (NF). Measurements from the receiver implemented in 65 nm CMOS show 70 dB of gain, NF as low as 3 dB, and 25 dBm out-of-band IIP3. Furthermore, tunable impedance matching shows that S11 <;- 30 dB can be achieved at any receive frequency from 0.1-1.3 GHz.

A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface

In this paper, a class of passive mixer-first, LNA-less receivers is analyzed in depth. Quadrature passive mixers are shown to present the impedance of their baseband port to the RF port and vice versa. This transparency property, in combination with resistive feedback differential amplifiers, and “complex” feedback between the I and Q paths, can be used to control the impedance at the RF port. This impedance can be tuned using only baseband components (i.e., resistors). The noise limits of such an architecture are analyzed and simulated, and are shown to be comparable to standard RF-LNA-first receivers. Accounting for the higher harmonics of the LO frequency proves critical in accurately analyzing the behavior of these circuits and their ability to provide an impedance match with low noise figure. Additionally, it is shown that expanding quadrature passive mixers to harmonic rejection mixers allows for even better noise performance and wider matching range.

Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers

This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands (I, II, III, IV, V, VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The receiver is part of a single-chip SAW-less transceiver reference platform IC for mass-market smartphones, which has been designed to meet Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The novel receiver core consists of a single-stage transconductance amplifier (TCA) with large gain control range, a current commutating passive mixer enhanced for automatic on chip IIP2 calibration with 25% duty-cycle LO injection and threshold adjust, and current-input complex Direct Coupled Filter (DCF). The low noise TCAs are designed without inductive loads to save area. A self-contained on chip automatic IIP2 calibration system with algorithm routine, implemented in firmware, is used to optimize IIP2 performance. This topology eliminates the external LNA, inter-stage SAW filter and transimpedance amplifier (TZA) in conventional WCDMA designs and results in current drain and die area savings as well as improved noise. The 25% duty-cycle LO injection, with threshold adjustment, into a current driven passive double-balanced mixer results in 3 dB additional gain, lower noise figure and lower intermodulation distortion. Large signal blocking and 1/f noise performance are improved significantly by eliminating the 0 and 180deg LO signal crossover at the mixer. The full receiver achieves 2.2 dB/2.39 dB simplex/duplex NF (with - 24.5 dBm TX leakage), > 90 dBm complex two-tone IIP2, 60 dB gain and - 1/+ 5 dBm half/full-duplex image IIP3. The receiver core consumes only 15.1 mA from a 1.5 V supply.

A Single–Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and ${+}$ 90 dBm IIP2

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

The performance of zero-IF receivers with current-driven passive mixers driven by 25% duty-cycle quadrature clocks is studied and analyzed. It is shown that, in general, these receivers outperform the ones that utilize passive mixers with 50% duty-cycle clocks. The known problems in receivers with 50% duty-cycle mixers, such as having unequal high- and low-side conversion gains, unexpected IIP2 and IIP3 numbers, and IQ crosstalk, are significantly lowered due to the operating principles of the 25% duty-cycle passive mixer. It is revealed that with an intelligent sizing of the design parameters, the 25%-duty-cycle-mixer-based receiver is superior in terms of linearity, noise, and elimination of IQ crosstalk.

Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm2, or 0.23 mm2 when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.

A 5.4 mW/0.07 mm $^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

The aim of the 2.4GHz front-end receiver presented in this paper is the minimization of both cost and energy consumption, focusing on WPAN IEEE 802.15.4 transceivers. It includes the entire RF part, from the balun to the first stage of the channel filter, as well as the LO signal conditioning cells. The proposed architecture uses an unmatched inductorless LNA and a new clocking scheme on a standard passive mixer. Compared to previously reported IEEE 802.15.4 receivers, an area reduction by at least 70% is achieved. The power consumption is relatively low at 5.4mW with a state-of-the-art noise and linearity performance. The receiver front-end operates at 1.35V. It is implemented in a 90nm CMOS technology using two thick metals, and alucap with RFMOM capacitors.

L. Garcia

Papers

A 5.4 mW/0.07 mm $^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

A 5.4mW 0.07mm 2 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN