VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating the minimum single stuck at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits.

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Test set compaction algorithms for combinational circuits

We propose a new scheme for built-in test (BIT) that uses multiple-polynomial linear feedback shift registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10/sup -6/. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage. >

Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.

Techniques for minimizing power dissipation in scan and combinational circuits during test application

Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >

COMPACTEST: a method to generate compact test sets for combinational circuits

Compactest: a method to generate compact test sets for combinational circuits

In this paper, the authors consider the problem of reducing the test set sizes for single stuck-at faults in combinational logic circuits. They report on an alternative to the conventional reverse order fault simulation, called reverse order test compaction (ROTCO). The proposed procedure processes a test set obtained by an existing test generator, with the sim of reducing the test set size. Unlike reverse order fault simulation, the proposed procedure allows the test vectors to be changed in order to increase the flexibility in detecting faults detected by earlier vectors, thereby potentially removing tests that cannot be removed by reverse order fault simulation. Experimental results for ISCAS-85 and PLA benchmark circuits are presented to demonstrate the effectiveness of the proposed procedure. >

ROTCO: a reverse order test compaction technique

A fault simulator for path delay faults in synchronous sequential circuits is described, where a test sequence is considered under different combinations of slow and fast clock cycles (clocking schemes). The features of the simulator are: (1) multiple clocking schemes used for the application of a given test sequence are considered in parallel, allowing fast fault simulation for a given sequence, to obtain the highest fault coverage achieveable by every sequence; (2) during the simulation process, it is possible to determine the clocking scheme so as to minimize the number of different clocking schemes to be used with the sequence, without compromising the fault coverage; and (3) a path representation scheme that allows efficient access to path delay faults detected by previous tests is used. Experimental results are presented to demonstrate these features and their effectiveness. >

SPADES: a simulator for path delay faults in sequential circuits

In this paper, we consider the problem of generating small (compact) test sets for single transition and CMOS stuck-open faults in combinational logic circuits. In addition, we propose that to generate test sets that cover a wide range of physical defects, a test set to detect faults of different models should be derived. Specifically, we address the problem of generating small and comprehensive test sets by considering the CMOS stuck-open and the single transition fault models together. We propose a dynamic test compaction technique for two-pattern tests, which exploits the test compaction strategies developed for stuck-at faults, and performs dynamic test vector overlap to derive small test sets. We present experimental results for ISCAS-85 combinational circuits and fully scanned versions of ISCAS-89 sequential circuits to illustrate the efficacy of the proposed test compaction technique.

L.N. Reddy

Papers

COMPACTEST: a method to generate compact test sets for combinational circuits

Compactest: a method to generate compact test sets for combinational circuits

ROTCO: a reverse order test compaction technique

SPADES: a simulator for path delay faults in sequential circuits

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits