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Irith Pomeranz
Researcher at Purdue University
Publications - 712
Citations - 10855
Irith Pomeranz is an academic researcher from Purdue University. The author has contributed to research in topics: Fault coverage & Automatic test pattern generation. The author has an hindex of 47, co-authored 682 publications receiving 10407 citations. Previous affiliations of Irith Pomeranz include University of Iowa.
Papers
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Journal ArticleDOI
Techniques for minimizing power dissipation in scan and combinational circuits during test application
TL;DR: Heuristics with good performance bounds can be derived for combinational circuits tested using built-in self-test (BIST) and considerable reduction in power dissipation can be obtained using the proposed techniques.
Journal ArticleDOI
COMPACTEST: a method to generate compact test sets for combinational circuits
TL;DR: Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCas-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposedHeuristics.
Proceedings ArticleDOI
Transient-fault recovery for chip multiprocessors
TL;DR: It is shown that CRTR incurs negligible performance loss compared to CRT for inter-processor (one-way) latency as high as 30 cycles, and that the bandwidth requirements of CRT and CRTR with DDBCE are 5.2 and 7.1 bytes/cycle, respectively.
Journal ArticleDOI
Transient-fault recovery using simultaneous multithreading
TL;DR: A scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) is proposed that enhances a previously proposed scheme for Transient-Fault detection, called Sim concurrently andRedundant Threaded (SRT) processors.
Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.