Proceedings ArticleDOI
Compactest: a method to generate compact test sets for combinational circuits
Irith Pomeranz,L.N. Reddy,Sudhakar M. Reddy +2 more
- pp 194-203
TLDR
Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed and can be added to existing test pattern generators without compromising fault coverage.Abstract:
Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >read more
Citations
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Proceedings ArticleDOI
Test set compaction algorithms for combinational circuits
Ilker Hamzaoglu,Janak H. Patel +1 more
TL;DR: In this paper, two new algorithms, redundant vector elimination (RVE) and essential fault reduction (EFR), were proposed for generating compact test sets for combinational circuits under the single stuck at fault model.
Journal ArticleDOI
Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
TL;DR: A new scheme for built-in test that uses multiple-polynomial linear feedback shift registers (MP-LFSR's) and an implicit polynomial identification reduces the number of extra bits per seed to one bit is presented.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
References
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Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Proceedings ArticleDOI
Combinational profiles of sequential benchmark circuits
F. Brglez,D. Bryan,K. Kozminski +2 more
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Journal ArticleDOI
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
TL;DR: PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits that uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems and is significantly more efficient than DALG over the general spectrum of combinational Logic circuits.
Journal ArticleDOI
Diagnosis of automata failures: a calculus and a method
TL;DR: The problem considered is the diagnosis of failures of automata, specifically, failures that manifest themselves as logical malfunctions, and an algorithm is developed which utilizes this calculus to compute tests to detect failures.
Proceedings ArticleDOI
A logic design structure for LSI testability
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.