Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main bottleneck is foreseen to migrate from computation to communication, efficient and scalable means of inter-core communication are crucial for guaranteeing steady performance improvements in many-core processors. As the number of cores grows, it remains unclear whether initial proposals, such as the Network-on-Chip (NoC) paradigm, will meet the stringent requirements of this scenario. This position paper presents a new research area where massive multicore architectures have wireless communication capabilities at the core level. This goal is feasible by using graphene-based planar antennas, which can radiate signals at the Terahertz band while utilizing lower chip area than its metallic counterparts. To the best of our knowledge, this is the first work that discusses the utilization of graphene-enabled wireless communication for massive multicore processors. Such wireless systems enable broadcasting, multicasting, all-to-all communication, as well as significantly reduce many of the issues present in massively multicore environments, such as data coherency, consistency, synchronization and communication problems. Several open research challenges are pointed out related to implementation, communications and multicore architectures, which pave the way for future research in this multidisciplinary area.

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Graphene-enabled wireless communication for massive multicore architectures

Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power consumption while improving performance. However, research has shown that power consumption and wiring complexity will be two of the major constraints that will hinder the growth of future NoCs architecture. This has resulted in the investigation of emerging technologies and devices to alleviate the power and performance bottleneck in NoCs. In this paper, we propose iWISE, an inter-router wireless scalable express channels for NoCs architecture that minimizes the power consumption via hybrid wireless communication channels, reduces the area overhead with smaller routers and shared buffers, and improves performance by minimizing the hop count. We compared our network to leading electrical and wireless topologies such as mesh, concentrated mesh, flattened butterfly and other wireless hybrid topologies. Our simulation results on real applications such as Splash-2, PARSEC, and SPEC2006 for 64 core architectures indicate that we save 2X power and 2X area while improving performance significantly. We show that iWISE can be further scaled to 256 cores while achieving a 2.5X performance increase and saving of 2X power when compared to other wireless networks on synthetic workloads.

iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture

With the rise of chip multiprocessors, an energy-efficient communication fabric is required to satisfy the data rate requirements of future multi-core systems. The Network-on-Chip (NoC) paradigm is fast becoming the standard communication infrastructure to provide scalable inter-core communication. However, research has shown that metallic interconnects cause high latency and consume excess energy in NoC architectures. Emerging technologies such as on-chip wireless interconnects can alleviate the power and bandwidth problems of traditional metallic NoCs. In this paper, we propose A-WiNoC , a scalable, adaptable wireless Network-on-Chip architecture that uses energy efficient wireless transceivers and improves network throughput by dynamically re-assigning channels in response to bandwidth demands from different cores. To implement such adaptability in our network at run-time, we propose an adaptable algorithm that works in the background along with a token sharing scheme to fully utilize the wireless bandwidth efficiently. Since no wireless NoC design has been completely realized with current technology, we describe technology trends in designing energy-efficient wireless transceivers with emerging technologies. We compare our proposed A-WiNoC to both wireless and wired topologies at 64 cores, with results showing a 1.4-2.6 $\times$ speedup on real applications and a 54 percent improvement in throughput for synthetic traffic. Using Synopsys Design Compiler, our results indicate that A-WiNoC saves 25-35 percent energy over other state-of-the-art networks. We show that A-WiNoC can scale to 256 cores with an energy improvement of 21 percent and a saturation throughput increase of approximately 37 percent.

A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors

Wireless networks-on-chips (WINoCs) hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. As the number of cores per IC grows, intercore communication requirements will also grow, and WINoCs can be used to both save power and reduce latency. In this article, we briefly describe some of the key challenges with WINoC implementation, and also describe our example design, iWISE, which is a scalable wireless interconnect design. We show that the integration of wireless interconnects with wired interconnects in NoCs can reduce overall network power by 34 percent while achieving a speedup of 2.54 on real applications.

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Wireless networks-on-chips: architecture, wireless channel, and devices

This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient ( $\sim ~1$ pJ/bit) transceivers over extremely short (≤ 100 cm) ranges. In an attempt to design such wireless interconnects, first a model for the wireless communication channel properties is developed. The use of CMOS-based energy-efficient on–off keying (OOK) transceiver architectures operating in the 60–90 GHz bands is considered as a practical solution. In order to address strict performance requirements of wireless HPC interconnects, and taking advantage of the recent developments in device scaling, compact low-power and innovative circuits based on novel double-gate MOSFETs (DG-MOSFETs) are proposed in the implementation of the architecture. The performance of a compact low-noise amplifier (LNA) design using common source (CS) inductive degeneration with 32 nm DG-MOSFETs is investigated by quantitative analysis and simulation. The proposed inductor-less two-stage cascode cascade LNA is optimized for 90 GHz operation and has the advantage of gain switching over its CMOS counterpart without the use of additional switching transistors, which makes it remarkably power efficient and faster. As further examples of efficient and compact DG-MOSFET circuits for OOK transceiver design, a three-stage CS 5 dB tunable power amplifier operating up to 90 GHz, and a novel 90 GHz voltage controlled oscillator are also presented. This is followed by the proposal of an array of four monopole antennas studied using full-wave EM solver.

A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects

This article advocates the use of short-range wireless communication inside a computing chassis. Ultrawideband links make it possible to design a within-chassis wireless interconnect. In contrast to conventional, fixed, wireline connections between chips, wireless communications offer certain unique advantages, as the authors explain.

Lei Guo

Papers

Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges