Showing papers by "Lei Yao published in 2019"
TL;DR: A fully implantable neural recording IC with a spike-driven data compression scheme to improve the power efficiency and preserve crucial data for monitoring brain activities and successfully demonstrated precise spike detection through both in vitro and in vivo acquisition of the neural signal.
Abstract: We present a fully implantable neural recording IC with a spike-driven data compression scheme to improve the power efficiency and preserve crucial data for monitoring brain activities. A difference between two consecutive neural signals, $\Delta $ -neural signal, is sampled in each channel to reduce the full dynamic range and the required resolution of an analog-to-digital converter (ADC), enabling the whole analog chain to be operated at a 0.5-V supply. A set of multiple $\Delta $ -signals are stored in analog memory to extract the magnitude and frequency features of the incoming neural signals, which are utilized to discriminate spikes in these signals instantaneously after the acquisition in the analog domain. The energy- and area-efficient successive approximation ADC is implemented and only converts detected spikes, decreasing the power dissipation and the amount of neural data. A prototype 16-channel neural interface IC was fabricated using a 0.18-μm CMOS process, and each component in the analog front-end was fully characterized. We successfully demonstrated precise spike detection through both in vitro and in vivo acquisition of the neural signal. The prototype chip consumed 0.88 μW/channel at a 0.5-V supply for the recording and compressed about 89% of neural data, saving the power consumption and bandwidth in the system.
30 citations
TL;DR: The proposed SFE IC adopts an eight-channel H-bridge structure with an integrated voltage compliance monitoring circuit based on triode detection of a sensing MOSFET and it shows the detection accuracy of 45mV from its measurement results.
Abstract: The proposed SFE IC adopts an eight-channel H-bridge structure with an integrated voltage compliance monitoring circuit. It has stimulation current ranged from 0.78mA to 6.2mA selected by 3b control and the stimulation current level can be controlled with 7b resolution within a selected current range. The current range can be expanded by using a high current option ranged from 2.71mA to 21.7mA under 3b control. The worst DNL and INL of the stimulation current source are 0.32 LSB and 0.3 LSB, respectively, from all the current ranges. The average mismatch between the cathodic and anodic current pulses in a biphasic stimulus is measured as 0.034% without using charge balancing techniques. The voltage compliance monitoring circuit is based on triode detection of a sensing MOSFET and it shows the detection accuracy of 45mV from its measurement results. The maximum steady-state voltage across the electrodes/ solution interface (resting potential) is also rigorously analyzed and verified through bench-top and saline experiments by utilizing the proposed stimulator. The SFE IC was fabricated in $0.18~\mu \text{m}$ 24 V CMOS process.
3 citations