Showing papers in "IEEE Transactions on Circuits and Systems I-regular Papers in 2019"

Asynchronous Finite-Time Filtering of Networked Switched Systems and its Application: an Event-Driven Method

Abstract: To effectively use the network resources, a suitable event-driven communication scheme is proposed for the networked switched systems in this paper. Under the EDCS, a finite-time filter is designed for switched systems, which does not synchronize with the switched systems. Different from the existing finite-time problems, finite-time boundedness (FTBs) and input–output finite-time stability (IO-FTSy) are simultaneously considered in this paper. Some sufficient conditions are established to check the properties of the FTBs and the IO-FTSy of the event-driven asynchronous filtering error system by constructing a reasonable Lyapunov–Krasovskii functional and using the average dwell time approach. All the matrix inequalities can be converted to linear matrix inequalities so as to design the event-driven asynchronous filter. The applicability of the proposed filtering scheme is demonstrated via a mass-spring system model.

Network-Based Quantized Control for Fuzzy Singularly Perturbed Semi-Markov Jump Systems and its Application

Abstract: This paper deals with the quantized control problem for nonlinear semi-Markov jump systems subject to singular perturbation under a network-based framework. The nonlinearity of the system is well solved by applying Takagi–Sugeno (T-S) fuzzy theory. The semi-Markov jump process with the memory matrix of transition probability is introduced, for which the obtained results are more reasonable and less limiting. In addition, the packet dropouts governed by a Bernoulli variable and the signal quantization associated with a logarithmic quantizer are deeply studied. The major goal is to devise a fuzzy controller, which not only assures the mean-square $\bar { \sigma }$ -error stability of the corresponding system but also allows a higher upper bound of the singularly perturbed parameter. Sufficient conditions are developed to make sure that the applicable controller could be found. The further examination to demonstrate the feasibility of the presented method is given by designing a controller of a series DC motor model.

Dynamic Analysis of Digital Chaotic Maps via State-Mapping Networks

Abstract: Chaotic dynamics is widely used to design pseudo-random number generators and for other applications, such as secure communications and encryption. This paper aims to study the dynamics of the discrete-time chaotic maps in the digital (i.e., finite-precision) domain. Differing from the traditional approaches treating a digital chaotic map as a black box with different explanations according to the test results of the output, the dynamical properties of such chaotic maps are first explored with a fixed-point arithmetic, using the Logistic map and the Tent map as two representative examples, from a new perspective with the corresponding state-mapping networks (SMNs). In an SMN, every possible value in the digital domain is considered as a node and the mapping relationship between any pair of nodes is a directed edge. The scale-free properties of the Logistic map’s SMN are proved. The analytic results are further extended to the scenario of floating-point arithmetic and for other chaotic maps. Understanding the network structure of a chaotic map’s SMN in digital computers can facilitate counteracting the undesirable degeneration of chaotic dynamics in finite-precision domains, also helping to classify and improve the randomness of pseudo-random number sequences generated by iterating the chaotic maps.

A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication

Abstract: Approximate computing is an emerging approach for reducing the energy consumption and design complexity in many applications where accuracy is not a crucial necessity. In this study, ultra-efficient imprecise 4:2 compressor and multiplier circuits as the building blocks of the approximate computing systems are proposed. The proposed compressor uses only one majority gate which is different from the conventional design methods using AND - OR and XOR logics. Furthermore, the majority gate is the fundamental logic block in many of the emerging majority-friendly nanotechnologies such as quantum-dot cellular automata ( QCA ) and single-electron transistor ( SET ). The proposed circuits are designed using FinFET as a current industrial technology and are simulated with HSPICE at 7nm technology node. The results indicate that our imprecise compressor is superior to its previous counterparts in terms of delay, power consumption, power delay product (PDP) and area, and improves these parameters on average by 32%, 68%, 78%, and 66%, respectively. In addition, the proposed efficient approximate multiplier is utilized in image multiplying as an important image processing application. The HSPICE and MATLAB simulations indicate that the proposed inexact multiplier provides a significant compromise between accuracy and design efficiency for approximate computing.

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

Abstract: Computing-in-memory (CIM) is a promising approach to reduce the latency and improve the energy efficiency of deep neural network (DNN) artificial intelligence (AI) edge processors. However, SRAM-based CIM (SRAM-CIM) faces practical challenges in terms of area overhead, performance, energy efficiency, and yield against variations in data patterns and transistor performance. This paper employed a circuit-system co-design methodology to develop a SRAM-CIM unit-macro for a binary-based fully connected neural network (FCNN) layer of the DNN AI edge processors. The proposed SRAM-CIM unit-macro supports two binarized neural network models: an XNOR neural network (XNORNN) and a modified binary neural network (MBNN). To achieve compact area, fast access time, robust operations, and high energy-efficiency, our proposed SRAM-CIM uses a split-wordline compact-rule 6T SRAM and circuit techniques, including a dynamic input-aware reference generation (DIARG) scheme, an algorithm-dependent asymmetric control (ADAC) scheme, a write disturb-free (WDF) scheme, and a common-mode-insensitive small offset voltage-mode sensing amplifier (CMI-VSA). A fabricated 65-nm 4-Kb SRAM-CIM unit-macro achieved 2.4- and 2.3-ns product-sum access times for a FCNN layer using XNORNN and MBNN, respectively. The measured maximum energy efficiency reached 30.49 TOPS/W for XNORNN and 55.8 TOPS/W for the MBNN modes.

Generating Multi-Scroll Chua’s Attractors via Simplified Piecewise-Linear Chua’s Diode

Abstract: High implementation complexity of multi-scroll circuit is a bottleneck problem in real chaos-based communication. Especially, in multi-scroll Chua’s circuit, the simplified implementation of piecewise-linear resistors with multiple segments is difficult due to their intricate irregular breakpoints and slopes. To solve the challenge, this paper presents a systematic scheme for synthesizing a Chua’s diode with multi-segment piecewise-linearity, which is achieved by cascading even-numbered passive nonlinear resistors with odd-numbered ones via a negative impedance converter. The traditional voltage mode op-amps are used to implement nonlinear resistors. As no extra DC bias voltage is employed, the scheme can be implemented by much simpler circuits. The voltage-current characteristics of the obtained Chua’s diode are analyzed theoretically and verified by numerical simulations. Using the Chua’s diode and a second-order active Sallen-Key high-pass filter, a new inductor-free Chua’s circuit is then constructed to generate multi-scroll chaotic attractors. Different number of scrolls can be generated by changing the number of passive nonlinear resistor cells or adjusting two coupling parameters. Besides, the system can be scaled by using different power supplies, satisfying the low-voltage low-power requirement of integrated circuit design. The circuit simulations and hardware experiments both confirmed the feasibility of the designed system.

Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

Abstract: In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about $2\times $ and $3.4\times $ the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of $\mu /\sigma $ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications.

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Abstract: The on-chip implementation of learning algorithms would speed up the training of neural networks in crossbar arrays. The circuit level design and implementation of a back-propagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we propose analog backpropagation learning circuits for various memristive learning architectures, such as deep neural network, binary neural network, multiple neural network, hierarchical temporal memory, and long short-term memory. The circuit design and verification are done using TSMC 180-nm CMOS process models and TiO2-based memristor models. The application level validations of the system are done using XOR problem, MNIST character, and Yale face image databases.

Event-Based Security Control for State-Dependent Uncertain Systems Under Hybrid-Attacks and Its Application to Electronic Circuits

Abstract: This paper investigates the problem of event-based security control for state-dependent uncertain systems under hybrid-attacks. An event-triggered scheme is adopted to mitigate the communication burden, where the sampled data are delivered only when the predefined triggering condition is violated. Meanwhile, a new hybrid-attacks model, which contains denial-of-service attacks and replay attacks, is established to describe the randomly occurring cyber-attacks. By taking hybrid-attacks into account, a novel mathematical model for state-dependent uncertain systems with event-triggered scheme is established. Then, through employing Lyapunov–Krasocskii stability theory and linear matrix inequality techniques, sufficient conditions ensuring the state-dependent uncertain systems being exponentially mean-square stable are deduced. Based on the derived sufficient conditions, the desired output feedback controller gain is obtained. Finally, the feasibility of the proposed method is demonstrated by a numerical example, and the applicability of the developed theoretical results is also illustrated by the controller design for electronic circuits.

Quantum Implementation Circuits of Quantum Signal Representation and Type Conversion

Abstract: Quantum signal processing offers a possible solution to store and process massive signals efficiently. As the foundation of quantum signal processing, quantum signal representation (QSR) that stores color information using basis states, is convenient to retrieve accurately signals from quantum systems. But the existing QSRs are only focus on integer signals (i.e., images) and are difficult to be directly operated by quantum Fourier transform (QFT) and quantum wavelet transform (QWT). Thus, we propose four models of QSR for integer, real, and complex signals. Furthermore, we design quantum implementation circuits of type conversions of QSR with complexity $O$ (1). Type conversions of QSR are illustrated by general processes of QFT and Haar QWT, and demonstrate that the proposed QSRs are suitable for QFT and QWT.

Ultra-Low Power QRS Detection and ECG Compression Architecture for IoT Healthcare Devices

Abstract: An ultra-low power electrocardiogram (ECG) processing architecture with an adequate level of accuracy is a necessity for Internet of Things (IoT) medical wearable devices. This paper presents a novel real-time QRS detector and an ECG compression architecture for IoT healthcare devices. An absolute-value curve length transform (A-CLT) is proposed that effectively enhances the QRS complex detection with minimized hardware resources. The proposed architecture requires adders, shifters, and comparators only, and removes the need for any multipliers. QRS detection was accomplished by using adaptive thresholds in the A-CLT transformed ECG signal, and achieved a sensitivity of 99.37% and the predictivity of 99.38% when validated using Physionet ECG database. Furthermore, a lossless compression technique was incorporated into the proposed architecture that uses the ECG signal first derivative and entropy encoding. An average compression ratio of 2.05 was achieved when evaluated using MIT-BIH database. The proposed QRS detection architecture deals with almost all the ECG signal artifacts, such as low-frequency noise, baseline drift, and high-frequency interference with minimum hardware resources. The proposed QRS architecture was synthesized using 65-nm low-power process using standard-cell-based flow. The power consumption of the design was 6.5 nW while operating at a supply of 1 V and a frequency of 250 Hz. Moreover, the system could benefit from duty-cycling.

SensorNet: A Scalable and Low-Power Deep Convolutional Neural Network for Multimodal Data Classification

Abstract: This paper presents SensorNet which is a scalable and low-power embedded deep convolutional neural network (DCNN), designed to classify multimodal time series signals. Time series signals generated by different sensor modalities with different sampling rates are first converted to images (2-D signals), and then DCNN is utilized to automatically learn shared features in the images and perform the classification. SensorNet: 1) is scalable as it can process different types of time series data with variety of input channels and sampling rates; 2) does not need to employ separate signal processing techniques for processing the data generated by each sensor modality; 3) does not require expert knowledge for extracting features for each sensor data; 4) makes it easy and fast to adapt to new sensor modalities with a different sampling rate; 5) achieves very high detection accuracy for different case studies; and 6) has a very efficient architecture which makes it suitable to be deployed at Internet of Things and wearable devices. A custom low-power hardware architecture is also designed for the efficient deployment of SensorNet at embedded real-time systems. SensorNet performance is evaluated using three different case studies including physical activity monitoring, stand-alone tongue drive system, and stress detection, and it achieves an average detection accuracy of 98%, 96.2%, and 94% for each case study, respectively. We implement SensorNet using our custom hardware architecture on Xilinx FPGA (Artix-7) which on average consumes 246- $\mu \text{J}$ energy. To further reduce the power consumption, SensorNet is implemented using application-specified integrated circuit at the post layout level in 65-nm CMOS technology which consumes approximately $8\times $ lower power compared to the FPGA implementation. In addition, SensorNet is implemented on NVIDIA Jetson TX2 SoC (CPU + GPU) and compared to TX2 single-core CPU and GPU implementations, FPGA-based SensorNet obtains $15\times $ and $4\times $ improvement in energy consumption.

Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays

Abstract: Deep neural networks are biologically inspired class of algorithms that have recently demonstrated the state-of-the-art accuracy in large-scale classification and recognition tasks. Hardware acceleration of deep networks is of paramount importance to ensure their ubiquitous presence in future computing platforms. Indeed, a major landmark that enables efficient hardware accelerators for deep networks is the recent advances from the machine learning community that have demonstrated the viability of aggressively scaled deep binary networks. In this paper, we demonstrate how deep binary networks can be accelerated in modified von Neumann machines by enabling binary convolutions within the static random access memory (SRAM) arrays. In general, binary convolutions consist of bit-wise exclusive-NOR (XNOR) operations followed by a population count (popcount). We present two proposals: one based on charge sharing approach to perform vector XNOR and approximate popcount and another based on bit-wise XNOR followed by a digital bit-tree adder for accurate popcount. We highlight the various tradeoffs in terms of circuit complexity, speed-up, and classification accuracy for both the approaches. Few key techniques presented as a part of the manuscript are the use of low-precision, low-overhead analog-to-digital converter (ADC), to achieve a fairly accurate popcount for the charge-sharing scheme and proposal for sectioning of the SRAM array by adding switches onto the read-bitlines, thereby achieving improved parallelism. Our results on benchmark image classification datasets for CIFAR-10 and SVHN on a binarized neural network architecture show energy improvements of up to $6.1\times $ and $2.3\times $ for the two proposals, compared to conventional SRAM banks. In terms of latency, improvements of up to $15.8\times $ and $8.1\times $ were achieved for the two respective proposals.

Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery

Abstract: Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Wallace multiplier optimized for speed, an $8\times 8$ AM1 using four most significant bits for error reduction shows a 60% reduction in delay (when optimized for delay) and a 42% reduction in power dissipation (when optimized for area). In a $16\times 16$ design, half of the least significant partial products are truncated for AM1 and AM2, which are thus denoted as TAM1 and TAM2, respectively. Compared with the Wallace multiplier, TAM1 and TAM2 save from 50% to 66% in power, when optimized for area. Compared with existing approximate multipliers, AM1, AM2, TAM1, and TAM2 show significant advantages in accuracy with a low power-delay product. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power.

Octave Bandwidth Doherty Power Amplifier Using Multiple Resonance Circuit for the Peaking Amplifier

Abstract: This paper presents a broadband Doherty power amplifier (DPA) design with an octave bandwidth based on a new load network consisting of a quasi-lumped impedance transformer for the carrier amplifier, a multiple resonance circuit for the peaking amplifier, and a broadband post-matching network. The quasi-lumped impedance transformer and the multiple resonance circuit were designed based on accurate equivalent circuits for internal components inside the packaged transistor. Based on power bandwidth analysis, optimum susceptance provided by the multiple resonance circuit at the peaking amplifier, was obtained. The proposed broadband DPA was designed using 45 W gallium–nitride high electron mobility transistor for both carrier and peaking amplifiers. For continuous-wave signals in frequency range of 0.9 to 1.8 GHz, the implemented broadband DPA exhibited a drain efficiency of 54.2% to 73.4% at peak output power of 49.7 to 51.4 dBm and a drain efficiency of 41.7% to 58.0% at output back-off of 6 dB. For the down-link long-term evolution signal with a channel bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, a drain efficiency of 41.3% to 57.4% and an adjacent channel leakage power ratio of −22.5 to −30.2 dBc at an average output power of 43.2 to 449 dBm were achieved at an octave bandwidth.

A 0.7-V 28-nW CMOS Subthreshold Voltage and Current Reference in One Simple Circuit

Abstract: This paper presents a low-power and high-precision voltage and current reference (VCR) in one simple circuit. The voltage reference is derived from the threshold voltage difference between an I/O (i.e., 3.3-V NMOS) and standard (i.e., 1.8-V NMOS) transistors with temperature-independent bias current, and the current reference is the voltage reference divided by a temperature-insensitive resistor. The resistor is made up by series connection of a proportional-to-absolute-temperature (PTAT) NWELL resistor and a complementary-to-absolute-temperature (CTAT) high-resistance poly resistor in series. Implemented in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCR circuit takes an active area of only 0.055 mm2. The measured voltage and current references ( $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ ) at room temperature are 368 mV and 9.77 nA, respectively. The measured average temperature coefficient (TC) of $\text{V}_{\mathrm {ref}}$ and $\text{I}_{\mathrm {ref}}$ are 43.1 ppm/°C and 149.8 ppm/°C over a temperature range of −40~125°C with one-time trimming and the variation coefficients are 0.35% and 1.6%, respectively. The measured voltage and current line sensitivities are 0.027%/V and 0.6%/V, respectively. The minimum supply voltage is 0.7 V with a total power consumption of 28 nW. The measured power supply ripple rejection (PSRR) of $\text{V}_{\mathrm {ref}}$ is −65 dB @DC and −39.4 dB at frequencies higher than 1 Hz.

ChipNet: Real-Time LiDAR Processing for Drivable Region Segmentation on an FPGA

Abstract: This paper presents a field-programmable gate array (FPGA) design of a segmentation algorithm based on convolutional neural network (CNN) that can process light detection and ranging (LiDAR) data in real-time. For autonomous vehicles, drivable region segmentation is an essential step that sets up the static constraints for planning tasks. Traditional drivable region segmentation algorithms are mostly developed on camera data, so their performance is susceptible to the light conditions and the qualities of road markings. LiDAR sensors can obtain the 3D geometry information of the vehicle surroundings with high precision. However, it is a computational challenge to process a large amount of LiDAR data in real-time. In this paper, a CNN model is proposed and trained to perform semantic segmentation using data from the LiDAR sensor. An efficient hardware architecture is proposed and implemented on an FPGA that can process each LiDAR scan in 17.59 ms, which is much faster than the previous works. Evaluated using Ford and KITTI road detection benchmarks, the proposed solution achieves both high accuracy in performance and real-time processing in speed.

An Integrated Discrete-Time Delay-Compensating Technique for Large-Array Beamformers

Abstract: This paper implements a wide aperture high-resolution true time delay for frequency-uniform beamforming gain in large-scale phased arrays. We propose a baseband discrete-time delay-compensating technique to augment the conventional phase-shift-based analog or hybrid beamformers. A generalized design methodology is first developed to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart for a given number of antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. This paper shows that delay-compensating analog or hybrid beamformers are more energy-efficient for high dynamic-range applications compared to true-time-delay digital beamformers. To demonstrate the feasibility of our proposed technique, a four-element analog delay-compensating baseband beamformer in 65-nm CMOS is prototyped. A time-interleaved switched-capacitor array implements the discrete-time delay-compensating beamformer with a wide delay range of 15-ns and 5-ps resolution. Measured power consumption is 47 mW with frequency-uniform array gain over 100-MHz modulated bandwidth, independent of angle of arrival. The proposed delay compensation scheme is scalable to accommodate the delay differences for large antenna arrays with higher range/resolution ENOB compared with prior art.

Pinning Synchronization of Complex Switching Networks With a Leader of Nonzero Control Inputs

Abstract: The evolution of the target system (leader) in pinning-controlled complex networks may need to be regulated by some control inputs for performing various practical tasks, e.g., obstacle avoidance, tracking highly maneuverable target, and so on. Motivated by this observation, we shall investigate the global pinning synchronization problems for complex switching networks for which the target system is subject to nonzero control inputs. First, using the idea of unit vector function method, a discontinuous coupling law is designed. With the aid of stability theory for switched systems, it is theoretically shown that synchronization in the network under this discontinuous coupling law can be achieved by choosing sufficiently large coupling strengths if the average dwell time (ADT) is bounded below by a positive constant. Second, we use the boundary layer method to design a continuous-coupling law. It has been theoretically shown that the synchronization error is ultimately uniformly bounded (UUB) under this continuous-coupling law. The chattering effect is also avoided in real implementation by using this continuous-coupling law. Furthermore, for networks with unknown external disturbances and unmodeled dynamics, neuro-adaptive-based coupling laws are designed to ensure that the synchronization error of the networks with undirected switching communication topologies under these laws is UUB. The obtained theoretical results are finally validated by performing numerical simulation on coupling Chua’s circuit systems.

Observer-Based Distributed Secure Consensus Control of a Class of Linear Multi-Agent Systems Subject to Random Attacks

Abstract: This paper is concerned with an observer-based distributed secure consensus control strategy for a class of linear multi-agent systems (MASs) with random attacks. Due to the fact that not all state information is available, observers are employed to estimate the internal states. The communication topology is randomly switching under the attacks, and a distributed secure consensus strategy is proposed using the output information. The feedback gains are calculated via solving the Riccati equation and Riccati inequality, and stability analysis is proven that the MAS achieves secure consensus tracking in the mean square sense. Finally, two examples are provided to verify the effectiveness of the observer-based control strategy.

Fault Estimation Observer Design for Descriptor Switched Systems With Actuator and Sensor Failures

Abstract: This paper is concerned with the fault estimation (FE) problem for continuous-time descriptor switched systems with unknown external disturbances, actuator, and sensor faults. In this paper, the multiplicative actuator fault is decoupled into the normal term and the fault term, where the actuator fault term and sensor faults can be extended into a new augmented vector. Then, a novel FE approach is developed for descriptor switched systems subject to the switching actions and state-inconsistence phenomena. By the parameter design, the proposed method can eliminate the effect of faults and disturbances, and achieve the accurate estimations of states and faults simultaneously. Finally, an example of circuit system is presented to show the effectiveness of the proposed method.

A Family of Stateful Memristor Gates for Complete Cascading Logic

Abstract: The conditional switching of memristors to execute stateful implication logic is an example of in-memory computation to potentially provide high energy efficiency and improved computation speed by avoiding the movement of data back and forth between a processing chip and memory and/or storage. Since the first demonstration of memristor implication logic, a significant goal has been to improve the logic cascading to make it more practical. Here, we describe and experimentally demonstrate nine symmetry-related Boolean logic operations by controlling conventional Ta/TaOx/Pt memristors integrated in a crossbar array with applied voltage pulses to perform conditional SET or RESET switching involving two or three devices, i.e., a particular device is switched depending on the state of another device. We introduce a family of four stateful two-memristor logic gates along with the copy and negation operations that enable two-input-one-output complete logic. In addition, we reveal five stateful three-memristor gates that eliminate the need for a separate data copy operation, decreasing the number of steps required for a particular task. The diversity of gates made available by simply applying coordinated sequences of voltages to a memristor crossbar memory significantly improves stateful logic computing efficiency compared to similar approaches that have been proposed.

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

Abstract: The conventional six-transistor static random access memory (SRAM) cell allows high density and fast differential sensing but suffers from half-select and read-disturb issues. Although the conventional eight-transistor SRAM cell solves the read-disturb issue, it still suffers from low array efficiency due to deterioration of read bit-line (RBL) swing and $\text{I}_{\mathbf {on}}/\text{I}_{\mathbf {off}}$ ratio with increase in the number of cells per column. Previous approaches to solve these issues have been afflicted by low performance, data-dependent leakage, large area, and high energy per access. Therefore, in this paper, we present three iterations of SRAM bit cells with nMOS-only based read ports aimed to greatly reduce data-dependent read port leakage to enable 1k cells/RBL, improve read performance, and reduce area and power over conventional and 10T cell-based works. We compare the proposed work with other works by recording metrics from the simulation of a 128-kb SRAM constructed with divided-wordline-decoding architecture and a 32-bit word size. Apart from large improvements observed over conventional cells, up to 100-mV improvement in read-access performance, up to 19.8% saving in energy per access, and up to 19.5% saving in the area are also observed over other 10T cells, thereby enlarging the design and application gamut for memory designers in low-power sensors and battery-enabled devices.

Synchronization of Multi-Agent Systems With Time-Varying Control and Delayed Communications

Abstract: This paper investigates the synchronization problem of nonlinear multi-agent systems with time-varying control in the presence of transmission delay over a communication network. To facilitate the study, a novel delayed differential inequality with time-varying coefficients is first established. Then, the synchronization problem is recast into the stability problem of a delayed differential system with certain time-dependent parameter. A sufficient criterion is further formulated to guarantee the synchronization. The mathematical proof reveals that the time average of the control strength is crucial for reaching synchronization. Together with the agent dynamics and the topology, this average also governs the largest admissible delay. Moreover, the criterion is applied to synchronization problems with general on-off coupling under data sampling and delayed communications, respectively. Some useful corollaries are consequently deduced. Finally, numerical simulations are presented to illustrate the validity of our theoretical results.

Adaptive Double Event-Triggered Control for Linear Multi-Agent Systems With Actuator Faults

Abstract: This paper considers the adaptive double event-triggered consensus control problem for linear multi-agent systems subject to multiplicative and additive actuator faults. The control updates and the communication among agents at the current time are determined by the proposed double event-triggered mechanisms (ETMs), where two ETMs possess different triggering conditions and operate independently. In this case, the limited communication bandwidth is saved, and the control updates are also reduced. On the other hand, adaptive techniques are combined with event-triggered techniques to solve the fault-tolerant problem. Time-varying multiplicative and additive actuator faults are considered simultaneously, which is more general than some existing literature. The adaptive double event-triggered protocols are designed in two ways corresponding to different cases: 1) the network topology is completely known and 2) the topology is unknown. Both design methods can ensure the asymptotic consensus of multi-agent systems, and the Zeno behavior is excluded. Finally, a simulation example is given to illustrate the effectiveness of the theoretical analysis.

Bipartite Synchronization and Convergence Analysis for Network of Harmonic Oscillator Systems With Signed Graph and Time Delay

Abstract: This paper considers the distributed control problem for a network of harmonic oscillator systems with delayed velocity coupling and signed graph topology containing a directed spanning tree. In sharp contrast to the dynamical behaviors of traditional coupled harmonic oscillators over unsigned graphs, it is found that the considered signed network can exhibit some more interesting behaviors, including bipartite synchronization, stabilization, and convergent behavior. First, when the underlying graph is structurally balanced, some necessary and sufficient conditions in terms of coupling strength and time delay are established to achieve bipartite synchronization in the signed network. Then, under the assumption that the signed graph is structurally unbalanced, it is shown that the network state converges either to the origin or to a nontrivial trajectory. In particular, a novel approach is developed to explicitly determine the converged trajectory based on the left and right eigenvectors associated with the simple zero eigenvalue of the signed graph’s Laplacian matrix. Finally, the theoretical analysis is illustrated by some numerical examples.

Efficient CMOS Invertible Logic Using Stochastic Computing

Abstract: Invertible logic can operate in one of two modes: 1) a forward mode, in which inputs are presented and a single, correct output is produced, and 2) a reverse mode, in which the output is fixed and the inputs take on values consistent with the output. It is possible to create invertible logic using various Boltzmann machine configurations. Such systems have been shown to solve certain challenging problems quickly, such as factorization and combinatorial optimization. In this paper, we show that invertible logic can be implemented using simple spiking neural networks based on stochastic computing. We present a design methodology for invertible stochastic gates, which can be implemented using a small amount of CMOS hardware. We demonstrate that our design can not only correctly implement the basic gates with invertible capability but can also be extended to construct invertible stochastic adder and multiplier circuits. The experimental results are presented, which demonstrate the correct operation of synthesizable invertible circuitry performing both multiplication and factorization, along with fabricated ASIC measurement results for an invertible multiplier circuit.

CORDIC-SNN: On-FPGA STDP Learning With Izhikevich Neurons

Abstract: This paper proposes a neuromorphic platform for on-FPGA online spike timing dependant plasticity (STDP) learning, based on the COordinate Rotation DIgital Computer (CORDIC) algorithms. The implemented platform comprises two main components. First, the Izhikevich neuron model is modified for implementation using the CORDIC algorithm, simulated to ensure the model accuracy, described as hardware, and implemented on FPGA. Second, the STDP learning algorithm is adapted and optimized using the CORDIC method, synthesized for hardware, and implemented to perform on-FPGA online learning on a network of CORDIC Izhikevich neurons to demonstrate competitive Hebbian learning. The implementation results are compared with the original model and state-of-the-art to verify accuracy, effectiveness, and higher speed of the system. These comparisons confirm that the proposed neuromorphic system offers better performance and higher accuracy while being straightforward to implement and suitable to scale.

A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications

Abstract: Currently, there is a growing attention toward developing efficient hardware convolutional blocks for several applications such as computer vision or image processing. Recent works have shown that using binary values in convolutional blocks can considerably reduce the overall power consumption while achieving a high degree of accuracy. In parallel, some works employed resistive random-access memory (RRAM) as an in-memory accelerator to directly store the convolution kernels and perform analog dot product operations in the array, reducing the overall power consumption by limiting the number of memory accesses. However, such architecture is hampered by the limited resistance precision and large intrinsic variability of RRAMs. In this paper, we present a purely digital robust RRAM-based convolutional block using single-ended XNOR sensing capable of performing dot product operations in a single cycle. By carefully considering physical design and RRAM limitations at the 28-nm technology node, we show that at the circuit level, our architecture can tolerate a resistance window as low as 1.09, ensuring reliable operations even under a high RRAM variability ( $\sigma /\mu = 25\%$ for a resistance window between both states around 50). When integrated in ISAAC, a state-of-the-art learning accelerator, our block can reduce the power by $2.7\times $ while guaranteeing robust operations.

Design and Implementation of a 0.3-V Differential Difference Amplifier

Abstract: A new silicon realization of an ultra-low-voltage and ultra-low-power differential-difference amplifier (DDA) is presented in this paper The circuit combines the idea of non-tailed bulk-driven differential pairs with a partial positive feedback used for voltage gain boosting The DDA operates from $V_{\mathbf {DD}}$ ranging from 03 to 05 V For a 03-V version, the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 185 kHz, PSRR of 57 dB and the average slew-rate of 155 V/ms at 20 pF load capacitance, while consuming only 22 nW of power An instrumentation amplifier based on the proposed DDA showed the THD of 05 % for $V_{\mathbf {in}}=50$ mV $_{\mathbf {pp}}$ , and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V The circuit has been fabricated in a standard n-well $018~\mu \text{m}$ CMOS process from TSMC Chip test results agree with simulations A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions