In this paper, a novel meander split power/ground plane is proposed for reducing crosstalk between parallel lines crossing over it. The working mechanism of the meander split scheme is investigated by simulations and measurements. The LC equivalent circuit and transmission line model are developed for modeling interactions between the meander split and the signal lines. The proposed meander structure enhances electromagnetic coupling between split planes. The capacitive coupling across the split ensures signal integrity and magnetic coupling between adjacent finger shaped structures suppresses lateral wave propagation along the split gap, which in turn helps suppress the crosstalk. The effectiveness of the meander split remains valid over very wide frequency ranges (up to 9 GHz). Experimental results show that the proposed structure improves the signal quality and reduces the near/far end crosstalk over 30 dB and 50% in the frequency domain and time domain, respectively.

A Novel Meander Split Power/Ground Plane Reducing Crosstalk of Traces Crossing Over

It is necessary to reduce the crosstalk noise in high-speed signaling channels. In the channel routing area, the tabbed routing pattern is used to mitigate far-end crosstalk (FEXT), and the electrical length is controlled with a time domain reflectometer (TDR) and time domain transmission (TDT). However, unlike traditional channels having uniform width and space, the width and space of tabbed routing changes by segment, and the capacitance and inductance values of tabbed routing also change. In this paper, we propose a tabbed routing equivalent circuit modeling method using the segmentation approach. The proposed model was verified using 3D EM simulation and measurement results in the frequency domain. Based on the calculated inductance and capacitance parameters, we analyzed the insertion loss, FEXT, and self-impedance in the frequency domain, and TDT and FEXT in the time domain, by comparing the values of these metrics with and without tabbed routing. Using the proposed tabbed routing model, we analyzed tabbed routing with variations of design parameters based on self- and mutual-capacitance and inductance.

Modeling, Verification, and Signal Integrity Analysis of High-Speed Signaling Channel with Tabbed Routing in High Performance Computing Server Board

Crosstalk becomes a serious problem in microstrip design of printed circuit boards (PCBs) in DDR5. In high-density and high-speed PCBs, widening space or putting shielding between traces to mitigate crosstalk noise may become less effective, because of the limited space. This paper presents a simple and efficient crosstalk reduction approach by using coverlay coated microstrip lines. This coverlay is available in a variety of film and adhesive thicknesses, which is commonly used materials for the resistance welding transform in PCB production. Based on the simulated S-parameters, the FEXT keeps under −40 dB from dc to 16.0 GHz, and more than 24 dB reduction for FEXT at 3.2 GHz can be achieved by using the coverlay technology, in comparison with that of the initial microstrip lines. The measured results show that the peak FEXT voltage with coverlay can be decreased by 83% of that without coverlay. Moreover, when the experimental results are compared with the simulated results, good agreement can be observed, demonstrating the validity of the proposed design.

A Study of Coverlay Coated Microstrip Lines for Crosstalk Reduction in DDR5

The suppression of crosstalk by combining the defected microstrip structure (DMS) with step-shaped transmission lines is proposed to address the problem of crosstalk between microstrip lines of the printed circuit board. This method suppresses the crosstalk between the microstrip lines by constructing two step-shaped coupled microstrip lines and etching the designed G-shaped DMS on one of the microstrip lines. Simulation and actual measurement results show that the combination of Gshaped DMS and step-shaped transmission line can effectively suppress crosstalk and reduce the far-end crosstalk by approximately 20 dB in the frequency range of 4–5 GHz. The actual measurement results in the vector network analyzer coincide with the high-frequency structure simulator simulation results.

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G-Shaped Defected Microstrip Structure Based Method of Reducing Crosstalk of Coupled Microstrip Lines

This article investigated the effects of local solder-mask and overlay structure changes on crosstalk. This structure is based on a four-layer high-speed PCB on a computer DDR5 board. Our goal is to use the obtained simulation results to locate the optimal response that not only meets the performance requirements but is also robust to geometric changes caused by manufacturing tolerances. These two methods have a good correlation with the simulation results and show strong capabilities in the practical applications.

Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT

Far-end crosstalk (FEXT) can be a problem in the design of printed circuit boards (PCB) for the incoming fifth generation double data rate (DDR5). In this paper, a FEXT mitigation method is proposed. This method adds an additional layer of homogeneous dielectric substrate with or without metal to make the transmission line more homogeneous. Therefore, the capacitive crosstalk can cancel out more inductive crosstalk at the far end. In our research, transmission lines with or without tabbed routing are analyzed and simulated. Finally, the frequency-domain and time-domain simulated results show that, in straight line areas, the dielectric substrate without metal achieves higher crosstalk reduction, while in tabbed routing areas, substrate with metal achieves better performances.

Far-End Crosstalk Mitigation Using Homogeneous Dielectric Substrate in DDR5

With improvement in the speed and frequency of electronic circuits, far-end crosstalk (FEXT) problem in printed-circuit board (PCB) neighboring routes becomes one of most critical factors affecting signal quality. In this paper, the FEXT can be mitigated significantly by inserting rectangular-shape resonators (RSR) structures in the coupled microstrip transmission lines where defected microstrip structures (DMS) are etched on the lines. The frequency domain simulation of HFSS shows that the S 41 of this proposed structure is decreased more than 16dB around 3.2GHz, compared with the traditional signal routing. The time domain simulation of ADS shows that the peak of FEXT voltage of this structure is improved to 89% compared to the traditional signal routing. It has been successfully demonstrated by simulation and comparison with all previous techniques that, this novel technique gives the best optimum low values for the peak voltage of FEXT. Thus, there is a great potential in DDR5, where the requirement of the high density wiring design is even severe.

Far-End Crosstalk Mitigation for Microstrip Lines in High-Speed PCBs

With improvement in high-density and high-speed printed circuit boards (PCBs), far-end crosstalk (FEXT) problem is one of most critical factors affecting signal quality. This is main because the spacing between adjacent signal lines becomes very small, such as the PCB routes in the fifth generation double data rate technology (DDR5). In this paper, a new method is developed for the mitigation of FEXT in DDR5. First, we investigate two cases, i.e., tabs added on the signal lines and graphene-paraffin materials coated signal lines with tabs. From the simulated S-parameters, the associated FEXT can be suppressed in a very wide frequency range (0~16GHz). Then, graphene-paraffin material is added on signal lines with tabs to further improve the performance. The FEXT can be decreased more than 12dB around 3.2GHz, compared with the traditional signal routing. It has been demonstrated by the final results in both frequency and time domains that, our structure has succeeded in mitigating FEXT in DDR5, in comparison with previous techniques. Thus, this method has a great potential in FEXT mitigation in DDR5.

Far-End Crosstalk Mitigation in DDR5 Using Graphene-Paraffin Material Coated Signal Lines with Tabs

Far-end crosstalk (FEXT) between adjacent signal lines is one of the most critical factors affecting signal integrity (SI) in double data rate 5 (DDR5) printed circuit boards (PCBs). In this paper, a new method for FEXT reduction, based on mushroom structures thickened soldermask (MSTS) for coupled signal lines, is proposed and investigated. From the simulated S-parameters results, FEXT of this proposed method can be suppressed among a very wide frequency range. Additionally, the FEXT is decreased more than 25dB around the main frequency of DDR5, compared with the traditional signal routing. Finally, both frequency and time domains results show that our proposed method could significantly improve the performance of SI and dramatically reduce FEXT for DDR5 system designs.

FEXT Reduction Using Mushroom Structures Thickened Soldermask for DDR5 PCBs

With the increase of signal rate, differential interconnection becomes more and more widely used. However, when the differential pair is asymmetric in layout, e.g., bending lines, common mode noise will be produced in the circuit, which may further cause EMI problems. In this paper, an efficient method, i.e., combing a U-shaped complementary open loop defective ground structure (DGS) with adding slow wave structure at the inner bending line, is proposed to suppress the differential-to-common mode conversion and common-mode noise of right angle bend discontinuity for differential signaling. The simulation results show that the mode conversion can be reduced to less than - 50dB in the bandwidth from DC to 16GHz. Moreover, the common mode noise is also significantly suppressed.

Liang Zhang

Papers

Far-End Crosstalk Mitigation Using Homogeneous Dielectric Substrate in DDR5

Far-End Crosstalk Mitigation for Microstrip Lines in High-Speed PCBs

Far-End Crosstalk Mitigation in DDR5 Using Graphene-Paraffin Material Coated Signal Lines with Tabs

FEXT Reduction Using Mushroom Structures Thickened Soldermask for DDR5 PCBs

A U-shaped Complementary Open Loop Defective Ground Structure with Slow Wave Structure for Mode Conversion and Common Mode Noise Suppression