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Author

Jun Fan

Bio: Jun Fan is an academic researcher from Missouri University of Science and Technology. The author has contributed to research in topic(s): Equivalent circuit & Printed circuit board. The author has an hindex of 36, co-authored 482 publication(s) receiving 5641 citation(s). Previous affiliations of Jun Fan include Ulsan National Institute of Science and Technology & University of Missouri.


Papers
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Journal ArticleDOI
TL;DR: This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines, discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.
Abstract: This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines, discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.

186 citations

Patent
02 Apr 2012
TL;DR: In this article, a coaxial cable sensor device with periodic impedance discontinuities along the length of its cable is described, which can be used to measure temperature, pressure, strain, and acoustic waves in building structures.
Abstract: A coaxial cable sensor device with periodic impedance discontinuities along the length of its cable. The cable comprises an inner conductor, insulating material disposed around the length of the inner conductor, and an outer conductor disposed around the insulating material. The periodic impedance discontinuities are created by physical deformations or material alterations to at least one of the inner conductor, the outer conductor, and the insulating material. The sensor device may be used to measure temperature, pressure, strain, and acoustic waves in building structures, and is well suited for down-hole or underwater applications.

162 citations

Journal ArticleDOI
TL;DR: In this paper, an analytical model for vias and traces is presented for simulation of multilayer interconnects at the package and printed circuit board levels, which can be applied to efficiently simulate a wide range of structures.
Abstract: Analytical models for vias and traces are presented for simulation of multilayer interconnects at the package and printed circuit board levels. Vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. It is shown that the models can be applied to efficiently simulate a wide range of structures. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. By virtue of the modal decomposition, the proposed method is general enough to handle structures with mixed reference planes. For the first time, these models have been validated against full-wave methods and measurements up to 40 GHz. An improvement on the computation speed of at least two orders of magnitude has been observed with respect to full-wave simulations.

142 citations

Journal ArticleDOI
TL;DR: In this article, the via-plate capacitance for a via transition to a multilayer printed circuit board is evaluated analytically in terms of higher order parallel-plate modes.
Abstract: The via-plate capacitance for a via transition to a multilayer printed circuit board is evaluated analytically in terms of higher order parallel-plate modes. The Green's function in a bounded coaxial cavity for a concentric magnetic ring current is first derived by introducing reflection coefficients for cylindrical waves at the inner and outer cavity walls. These walls can be perfect electric conductor (PEC)/perfect magnetic conductor(PMC) or a nonreflective perfectly matched layer. By further assuming a magnetic frill current on the via-hole in the metal plate, an analytical formula is derived for the via barrel-plate capacitance by summing the higher order modes in the bounded coaxial cavity. The convergence of the formula with the number of modes, as well as with the radius of the outer PEC/PMC wall is discussed. The analytical formula is validated by both quasi-static numerical methods and measurements. Furthermore, the formula allows the investigation of the frequency dependence of the via-plate capacitance, which is not possible with quasi-static methods.

131 citations

Journal ArticleDOI
TL;DR: In this article, the authors investigated the effect of placing SMT capacitors in proximity to ICs in multilayer PCB designs and demonstrated that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias.
Abstract: Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

129 citations


Cited by
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[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

30,199 citations

DOI
03 Oct 2018

844 citations

01 Jan 2016

565 citations

Journal ArticleDOI
TL;DR: In this paper, the authors proposed a wideband ultra wideband (UWB) communication protocol with a low EIRP level (−41.3dBm/MHz) for unlicensed operation between 3.1 and 10.6 GHz.
Abstract: Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

452 citations