A fully integrated continuous-time low-pass filter has been fabricated with CMOS technology. The device implements an active RC network using integrated capacitors and MOS transistors operated in the nonsaturation region as voltage-controlled resistors. The filter topology is fully balanced for good linearity and for good power supply rejection. The cutoff frequency is voltage adjustable around 3 kHz, allowing compensation for process and temperature variations. For 5-V power supplies a dynamic range of over 94 dB has been achieved.

Fully integrated active RC filters in MOS technology

Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition.

Atomic layer deposition of CMOS gates with variable work functions

Low defect density oxides suitable for use as thin gate oxides or in charge storage capacitors are described. First and second layers are formed on a substrate with misaligned defect structures. A third layer is then grown by diffusing a species through the first and second layers to the substrate. The species reacts with the substrate. The low defect density results from the misaligned defect structure of the first and second layers. In one embodiment, the first and second layers are grown and deposited oxides, respectively. The third layer is grown by diffusing oxygen through the first two layers and the interface between the first and second layers acts as a sink trapping defects. The oxide silicon interface has desirable characteristics because the oxide grows in near equilibrium conditions.

Fabricating a semiconductor device with low defect density oxide

This paper proposes a new layout method for high-speed VLSI circuits in single-poly and double-metal MOS technology. With emphasis on the speed performance, our Metal-Metal Matrix (M /sup 3/) layout method employs maximal use of metal interconnections while restricting delay-consuming polysilicon or polycide features only to form MOS transistor gates or to connect the same type of transistor gates with common input signals. M /sup 3/ layout is also amenable to submicron technology trends and existing CAD tools for single-poly and single-metal chip assembly and routing. Our layout studies indicate that M /sup 3/ is particularly appealing to high-speed dynamic CMOS circuits in view of packing density and speed performance. This new structure has not been experimented with VLSI chip fabrication yet and awaits empirical verification.

Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout

A voice-band continuous-time filter is described which was designed based on the technique of fully balanced networks and was fabrication in a 3.5-/spl mu/ CMOS technology. The filter implements a fifth-order elliptic low-pass transfer function with 0.05-dB passband ripple and 3.4 kHz cutoff frequency. A phase-locked loop control system fabricated on the same chip automatically references the frequency response of the filter to an external fixed clock frequency. The cutoff frequency was found to vary by less than 0.1% for an operating temperature range of 0-85/spl deg/C. The absolute value accuracy of the cutoff frequency was 0.5% (standard deviation). With /spl plusmn/5-V power supplies the measured dynamic range of the filter was approximately 100 dB.

An elliptic continuous-time CMOS filter with on-chip automatic tuning

CMOS technology has been developed through several generations of design rules with an n-type substrate (where p-channel transistors were formed) and with a p-tub implanted and diffused region (where n-channel transistors were formed). In order to enable a separate optimization of both transistors and to utilize the dopant control available with implanted layers, a two-tub approach was adopted. Utilizing lightly doped epi on an n+substrate (for latch-up protection), nitride-masked self-aligned tubs, 1016cm-3surface doping and 600A gate oxides, an 8-mask CMOS process (named 'Twin-Tub") was formulated. The combination of n on n+epi and careful I/O layout renders the circuits latch-up free. Novel aspects of the process, the devices it produces and finally the resultant circuit performance are herein described.

Twin-tub CMOS - A technology for VLSI circuits

Disclosed is an eight-mask twin-tub CMOS process which forms contiguous p- and n-tubs in a relatively lightly doped bulk region in a self-aligned manner using a single masking step. The process also forms the sources and drains of the p- and n-channel transistors with a single masking step by first nonselectively implanting p-type impurities into all source and drain regions and then selectively implanting n-type impurities into only the source and drain regions of the n-channel transistors in amounts sufficient to overcompensate the p-type impurities therein.

Method for fabricating complementary field effect transistor devices

A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.

Process for forming complementary integrated circuit devices

To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic implants through a common mask, and the p-tub is made by two separate boron implants through a common mask, complementary to that used for forming the n-tub. One of the boron implants occurs before, the other after, the drive-in heating step. After tub formation, further movement of the implanted ions is kept small by use of a high pressure process for growing the field oxide and by only limited further heating. Transistors are then formed in the tubs.

CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well

We have developed a fine-line CMOS technology that uses a single-type, p+polycide (polysilicon/silicide) gate for both NMOS and PMOS transistors. This approach eliminates the problems encountered when using n- and p-type polysilicon gate for NMOS and PMOS transistors that have a common polycide gate. For the n- and p-type polysilicon gates under silicide structure, it has been found that extremely rapid lateral impurity diffusion occurs in the TaSi 2 upper layer of the polycide gate structure Such impurity diffusion alters the work functions of the adjacent NMOS and PMOS devices. With p+-polycide gates for both types of devices, the PMOS device is a "surface-channel" type, and the NMOS device is a (normally off) "buried-channel" type The PMOS device is less prone to punchthrough at short channel lengths than the NMOS device; however, the NMOS device performance benefits from the mobility enhancement of the buried-channel structure. We will highlight here the relativity advantages and disadvantages of the surface-and buried-channel NMOS devices. We describe the I-V characteristics of p+-polycide gate NMOS and PMOS transistors having 175A thick gate oxide, threshold voltages of ±0.7V and electrical channel lengths of 1.0µm.

Louis Carl Parrillo

Papers

Twin-tub CMOS - A technology for VLSI circuits

Method for fabricating complementary field effect transistor devices

Process for forming complementary integrated circuit devices

CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well

A fine-line CMOS technology that uses p + polysilicon/silicide gates for NMOS and PMOS devices