This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.

Nanoscale CMOS

Metal silicides have played an indispensable role in the rapid developments of microelectronics since PtSi was first used to improve the rectifying characteristics of diodes in early 1960s. This wo ...

Metal silicides in CMOS technology : Past, present, and future trends

A process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, non-homogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etching chamber 30. In the etching step, process gas comprising etchant gas is used to etch a substrate 25 in the etching chamber 30 thereby depositing etch residue inside the chamber 30. Cleaning gas is added to the process gas for a sufficient time and in a volumetric flow ratio that is sufficiently high, to react with and remove substantially all the etch residue deposited by the process gas. The present method advantageously cleans the etch residue in the chamber 30, during the etching process, and without use of separate cleaning, conditioning, and seasoning process steps.

Self-cleaning etch process

A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF 6 and Ar, the volumetric flow ratio of SF 6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF 4 and Ar, the volumetric flow ratio of CF 4 to other components of the second process gas being from about 1:0 to about 1:10.

Two-stage etching process

A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

Method for forming a transistor having silicided regions

A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi 2 source/drains with sheet resistivities of 1.5-2 Ω/square, n+ and p+ polysilicon/TaSi 2 gate structures, Threshold voltages of 0.4 V and 1.5 µm separation between active to tub-edge regions. Diode characteristics of the CoSi 2 /n+ and CoSi 2 /P+ are determined to be as good as non-silicided silicon junctions. Maintaining the proper doping for the connected n+ and p+ polysilicon/silicide gates is demonstrated. Ring oscillator delays of 110 ps at 3.5 V are observed for devices with 0.5 µm channel lengths. The ring oscillator circuits are still operational at power supply voltages of 1.0 V due to the low threshold voltage of the transistors.

A symmetric submicron CMOS technology

We have developed a fine-line CMOS technology that uses a single-type, p+polycide (polysilicon/silicide) gate for both NMOS and PMOS transistors. This approach eliminates the problems encountered when using n- and p-type polysilicon gate for NMOS and PMOS transistors that have a common polycide gate. For the n- and p-type polysilicon gates under silicide structure, it has been found that extremely rapid lateral impurity diffusion occurs in the TaSi 2 upper layer of the polycide gate structure Such impurity diffusion alters the work functions of the adjacent NMOS and PMOS devices. With p+-polycide gates for both types of devices, the PMOS device is a "surface-channel" type, and the NMOS device is a (normally off) "buried-channel" type The PMOS device is less prone to punchthrough at short channel lengths than the NMOS device; however, the NMOS device performance benefits from the mobility enhancement of the buried-channel structure. We will highlight here the relativity advantages and disadvantages of the surface-and buried-channel NMOS devices. We describe the I-V characteristics of p+-polycide gate NMOS and PMOS transistors having 175A thick gate oxide, threshold voltages of ±0.7V and electrical channel lengths of 1.0µm.

A fine-line CMOS technology that uses p + polysilicon/silicide gates for NMOS and PMOS devices

The microstructure and metal‐silicon work function was evaluated for polycrystalline Si (poly‐Si) films (∼3500 A) implanted with BF2, with and without a CoSi2 superlayer. The poly‐Si implant doses were 2, 4, and 6×1015 cm−2, activated at 800–950 °C, for various times. The work function is observed to be dependent upon the BF2 dose, the anneal time, the anneal temperature, and independent of the presence of a thin CoSi2 superlayer subsequently sintered on the poly‐Si. The work function is not affected by additional implants into a CoSi2 superlayer. The measured work function for this material is shifted to more positive values by penetration of boron from the gate, into the oxide and possibly into the substrate during a ≳900 °C activation cycle. The major correlation of CoSi2/poly‐Si interface roughness is with poly‐Si grain size. The interface becomes smoother as the poly‐Si grain size becomes smaller. Similarly, the maximum extent of CoSi2 asperities is less for Co sintered on BF2 implanted poly‐Si when ...

R.L. Field

Papers

A symmetric submicron CMOS technology

A fine-line CMOS technology that uses p + polysilicon/silicide gates for NMOS and PMOS devices

BF2 implanted polycrystalline silicon gates with and without CoSi2: Microstructure and work functions