We present a 32 times 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 mum times 56 mum , while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-mum CMOS process.

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A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems

Difficulty and challenges of implementing time-delay-integration (TDI) functionality in a CMOS technology are studied: synchronization of the samples forming a TDI pixel, adder matrix outside the array, and addition noise. Existing and new TDI sensor architecture concepts with snapshot shutter, rolling shutter, or orthogonal readout are presented. An optimization method is then introduced to inject modulation transfer function and quantum efficiency specification in the architecture definition. Moderate spatial and temporal oversamplings are combined to achieve near charge-coupled device (CCD) class performances, resulting in an acceptable design complexity. Finally, CCD and CMOS dynamic range and signal-to-noise ratio are conceptually compared.

Time-Delay-Integration Architectures in CMOS Image Sensors

Embodiments of the present invention include systems and methods for generating a curvature compensated bandgap voltage reference. In an embodiment, a curvature compensated bandgap reference voltage is achieved by injecting a temperature dependent current at different points in the bandgap reference voltage circuit. In an embodiment, the temperature dependent current is injected in the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) current generation block of the bandgap circuit. Alternatively, or additionally, the temperature dependent current is injected at the output stage of the bandgap circuit. In an embodiment, the temperature dependent current is a linear piecewise continuous function of temperature. In another embodiment, the temperature dependent current has opposite dependence on temperature to that of the bandgap voltage reference before curvature compensation.

Curvature compensated bandgap voltage reference

This paper presents a high frame rate linear scan CMOS image sensor (CIS) with time-delay integration (TDI) technique and interlaced super-resolution (ISR) pixel to increase signal-to-noise ratio (SNR) and horizontal resolution. An adjacent pixel signal transfer (APST) methodology is adopted for efficient wire routing and reducing pixel complexity. 4T-APS is applied in pixel to achieve the snapshot function. A 128×8×2 interlaced super-resolution pixel array with a pitch of 6×6 um2, a fill factor of 26.99%, and 3.3V operation has been designed and fabricated in 0.18-um TSMC 1P6M CIS technology. Two 128×8 linear array are placed in an interlaced form with a half-pixel-pitch shift to achieve the super-resolution output. The measurement results of proposed linear scan sensor with 8 TDI stages and ISR technique demonstrate a SNR improvement of 10.3 dB, double horizontal resolution, and a power dissipation of 4.114uW per column at 1.6kfps.

Linear CMOS image sensor with time-delay integration and interlaced super-resolution pixel

An improved complementary metal oxide semiconductor image sensor for time delay and integration imaging is provided that utilizes rolling shutter pixels. Columns of rolling shutter pixels in the CMOS image array are provided with a space between adjacent pixels to provide synchronization with movement of the subject in the along track direction. Preferably, the physical offset between the pixels is 1/Nth of a pixel pitch for a column having N rows.

CMOS TDI image sensor with rolling shutter pixels

A correlated double sample (CDS) stage design is proposed for CMOS image readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive switch capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports integration-while-read (IWR) mode, then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

Correlated double sample design for CMOS image readout IC

A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 674mw, which reduced more than 85% In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 05μm DPDM n-well CMOS process

Low Power Design of Column Readout Stage for 320x288 Snapshot Infrared ROIC

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.

Design of high performance CMOS linear readout integrated circuit

This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage Defective pixel correction is also implemented in this circuit The simulation results show that the TDI function is correctly implemented and the linearity is improved from 9615% to 9770% (without the common output stage) at the expense of a little increase of power dissipation

A TDI CMOS Readout Circuit for IRFPA with Linearity Improvement

A novel dual-window readout structure is presented in this paper The ROIC with this structure can work in two modes: normal mode and windowing mode The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode Furthermore, the positions and sizes of these sub-arrays can be specified by users This feature allows image system to trace two fast moving objects without using two ROICs An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 05/spl mu/m DPTM n-well CMOS process

Lu Wengao

Papers

Correlated double sample design for CMOS image readout IC

Low Power Design of Column Readout Stage for 320x288 Snapshot Infrared ROIC

Design of high performance CMOS linear readout integrated circuit

A TDI CMOS Readout Circuit for IRFPA with Linearity Improvement

The study of dual-window random addressable ROIC