Charge-Pump Phase-Locked Loops에 관한 연구 및 회로 설계

Embodiments of the present invention include systems and methods for generating a curvature compensated bandgap voltage reference. In an embodiment, a curvature compensated bandgap reference voltage is achieved by injecting a temperature dependent current at different points in the bandgap reference voltage circuit. In an embodiment, the temperature dependent current is injected in the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) current generation block of the bandgap circuit. Alternatively, or additionally, the temperature dependent current is injected at the output stage of the bandgap circuit. In an embodiment, the temperature dependent current is a linear piecewise continuous function of temperature. In another embodiment, the temperature dependent current has opposite dependence on temperature to that of the bandgap voltage reference before curvature compensation.

Curvature compensated bandgap voltage reference

A family of bandgap embodiments are disclosed herein, capable of operating with very low currents and low power supply voltages, using neither any custom devices nor any special manufacturing technology, and fabricated on mainstream standard digital CMOS processes. As such, manufacturing cost can be kept low, manufacturing yields of digital CMOS system-on-a-chip (SOC) that require a reference can be kept optimal, and manufacturing risk can be minimized due to its flexibility with respect to fabrication process node-portability. Although the embodiments disclosed herein use novel techniques to achieve accurate operations with low power and low voltage, this family of bandgaps also uses parasitic bipolar junction transistors (BJT) available in low cost digital CMOS process to generate proportional and complementary to absolute temperature (PTAT and CTAT) voltages via the base-emitter voltage (V EB ) of BJTs and scaling V EB differential pairs to generate the BJTs thermal voltage (V T ).

Ultra-low power and ultra-low voltage bandgap voltage regulator device and method thereof

Design and implementation of a micro-power CMOS voltage reference circuit based on thermal compensation of Vgs

A precision integrated bandgap voltage reference in 0.35 mum CMOS technology is here presented. The circuit uses natural npn bipolar transistors as reference diodes. A particular attention was paid to the compensation of the several offsets that could strongly influence the performances of the reference. A very simple sample and hold technique for offset compensation is here presented. The proposed technique is straight forward for all bandgap topologies which use diodes with a terminal connected to the ground node or to the supply node. The temperature coefficient (TC) of the generated output voltage is 12.7 ppm/degC versus about 245 ppm/degC of the same circuit without offset compensation. A full description and an analytical expression for the proposed compensation technique are given. The results of the most relevant simulations are also reported. The circuit has been inserted in a test chip whose layout is shown.

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An offset compensation technique for bandgap voltage reference in CMOS technology

This paper proposes a novel calibration technique and its application on an adaptive-bandwidth PLL The new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference directly The maximum calibration time is less than five comparison periods With the calibration technique and an adaptive bandwidth, the PLL can maintain optimal performance during the whole working range The proposed circuit has been implemented in 018 um CMOS logic process Results show that the calibration time is less than 12?s, and the total locking time is less than 3?s The PLL has good jitter performance within its operating range from 860 MHz to 21GHz

A novel calibration technique applying to an adaptive-bandwidth PLL

A novel dual-window readout structure is presented in this paper The ROIC with this structure can work in two modes: normal mode and windowing mode The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode Furthermore, the positions and sizes of these sub-arrays can be specified by users This feature allows image system to trace two fast moving objects without using two ROICs An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 05/spl mu/m DPTM n-well CMOS process

The study of dual-window random addressable ROIC

This paper presents a precise compensated bandgap reference without resistors This bandgap reference uses an improved voltage-transfer unit instead of resistors A current proportional to T/sup /spl alpha// (/spl alpha/ is a constant) is produced to compensate for the higher order of the V/sub EB/ This bandgap reference is based on 05/spl mu/m n-well CMOS technology The supply voltage is 5V, working from -10/spl deg/C to 90/spl deg/C, the effective temperature coefficient of the output voltage is only 7 ppm//spl deg/C, and the maximum power dissipation is 076mW

A precise compensated bandgap reference without resistors

A precise curvature compensated CMOS bandgap voltage reference is presented, which utilizes temperature-independent current and an improved voltage-transfer unit to compensate for the higher order of the VBE. The new proposed bandgap voltage reference is implemented in 0.13 mum CMOS technology and operates with 0.9V supply voltage consuming 48muW at room temperature. The circuit achieves 5ppm/degC of temperature coefficient with temperature range from -40 to 85degC. With 0.9V supply voltage, the power noise rejection ratio is -25 dB at 10 kHz

A Precise Curvature Compensated CMOS Bandgap Voltage Reference with Sub 1V Supply

This paper presents a low jitter adaptive-bandwidth charge pump PLL with an improved passive filter. With an adaptive bandwidth, the proposed PLL maintains optimal performance over its whole operating range. In order to improve the jitter performance of the PLL, matching technique is employed in the charge pump, and a voltage-to-voltage converter is used to achieve a low gain VCO. The novel circuit has been implemented in 0.35 mum CMOS process. Post simulation results show that the PLL can scale its loop dynamics proportional to the operating frequency and has good jitter performance within its operating range from 100 MHz to 1.1 GHz.

Song Ying

Papers

A novel calibration technique applying to an adaptive-bandwidth PLL

The study of dual-window random addressable ROIC

A precise compensated bandgap reference without resistors

A Precise Curvature Compensated CMOS Bandgap Voltage Reference with Sub 1V Supply

Design of low jitter adaptive-bandwidth charge pump PLL with passive filter