We present a 32 times 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 mum times 56 mum , while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-mum CMOS process.

/pdf/a-spatial-contrast-retina-with-on-chip-calibration-for-27qx47sder.pdf

A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems

Difficulty and challenges of implementing time-delay-integration (TDI) functionality in a CMOS technology are studied: synchronization of the samples forming a TDI pixel, adder matrix outside the array, and addition noise. Existing and new TDI sensor architecture concepts with snapshot shutter, rolling shutter, or orthogonal readout are presented. An optimization method is then introduced to inject modulation transfer function and quantum efficiency specification in the architecture definition. Moderate spatial and temporal oversamplings are combined to achieve near charge-coupled device (CCD) class performances, resulting in an acceptable design complexity. Finally, CCD and CMOS dynamic range and signal-to-noise ratio are conceptually compared.

Time-Delay-Integration Architectures in CMOS Image Sensors

A method of one aspect includes reading a reset level of an active pixel, and concurrently, reading a reset level of a reference pixel. The method also includes reading an image signal level of the active pixel, and concurrently, reading an image signal level of the reference pixel. A reduced noise image signal level of the active pixel is generated based on the reset levels and the image signal levels of the active and reference pixels. Other methods are disclosed as well as apparatus and systems.

Reducing noise in image sensors by concurrently reading reset and image signal levels from active and reference pixels

Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates
time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and
the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in
current domain by using switched current structures that reduces required area for chip and improves linearity
performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain
settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V
dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with
1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing
technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process.

/pdf/design-of-a-roic-for-scanning-type-hgcdte-lwir-focal-plane-27he5rxzby.pdf

Design of a ROIC for Scanning Type HgCdTe LWIR Focal Plane Arrays

Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions.

Automated conversion of synchronous to asynchronous circuit design representations

A correlated double sample (CDS) stage design is proposed for CMOS image readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive switch capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports integration-while-read (IWR) mode, then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

Correlated double sample design for CMOS image readout IC

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.

Design of high performance CMOS linear readout integrated circuit

A novel dual-window readout structure is presented in this paper The ROIC with this structure can work in two modes: normal mode and windowing mode The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode Furthermore, the positions and sizes of these sub-arrays can be specified by users This feature allows image system to trace two fast moving objects without using two ROICs An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 05/spl mu/m DPTM n-well CMOS process

The study of dual-window random addressable ROIC

A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 mW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 mW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 mm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.

A novel low-power readout structure for TDI ROIC

An op-amp with a push-pull output stage for infrared focal plane array (IRFPA) readout integrated circuit (ROIC) is described in this paper. It works in the class AB mode with little die area. The op-amp is simulated by the SMIC 0.35-/spl mu/m CMOS process. The circuit is designed to operate from a single 5 V power and drive a capacitive load of 15 pF. The unity gain-bandwidth (GBW) is 30 MHz. the rising slew rate (SR) 34 V/s. and the falling slew rate (SR-) 39 V/s. The common-mode input and the output swing are almost 5 V.

Cui Wentao

Papers

Correlated double sample design for CMOS image readout IC

Design of high performance CMOS linear readout integrated circuit

The study of dual-window random addressable ROIC

A novel low-power readout structure for TDI ROIC

An op-amp with novel push-pull output stage for IRFPA ROIC