International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Characterization adn reduction of variation for integrated circuits

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

A lithographic apparatus configured to project a patterned beam of radiation onto a target portion of a substrate is disclosed. The apparatus includes a first radiation dose detector and a second radiation dose detector, each detector comprising a secondary electron emission surface configured to receive a radiation flux and to emit secondary electrons due to the receipt of the radiation flux, the first radiation dose detector located upstream with respect to the second radiation dose detector viewed with respect to a direction of radiation transmission, and a meter, connected to each detector, to detect a current or voltage resulting from the secondary electron emission from the respective electron emission surface.

Lithographic apparatus, and device manufacturing method

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

A data storage medium contains mask layout data for use in writing a mask includes a first mask data portion which corresponds to a feature having an interior corner. The first mask data portion corresponding to the interior corner includes a multi-level or stepped inner serif in the interior corner which provides for improved writeability of OPC independent of process push or bias. Alternatively, the data storage medium contains mask layout data which includes a second mask data portion. The second mask data portion corresponds to a feature having an exterior corner and includes a multi-level or stepped outer serif on the exterior corner. The stepped outer serif also provides for improved writeability of OPC independent of process push or bias.

Modification of mask layout data to improve writeability of OPC

A method (100) of characterizing optical proximity correction designs includes performing a mathematical transform (160) on a first feature (150) and a second feature (167) each having a core portion (152) and a first OPC design and a second OPC design applied thereto, respectively. The method (100) further includes obtaining a metric (162) for the transformed first and second features, wherein the metric is based upon a capability of a pattern transfer system which will utilize masks employing the first and second features (150, 167) as a patterns thereon. One of the first feature or the second feature is then selected (170) based upon an application of the metric to the first and second transformed features (150, 167), thereby selecting the one of the first feature or the second feature which provides for a better pattern transfer performance.

Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion

The past decade has experienced a remarkable synergy between Resolution Enhancement Technologies (RET) in Optical Lithography and Optical Proximity Correction (OPC). This heterogeneous array of patterning solutions ranges from simple rule-based to more sophisticated model-based corrections, including sub-resolution assist features, partially transmitting masks and various dual mask approaches. A survey of the evolutionary development from the early introduction of the first OPC engines in 1996 to the debut of Immersion Lithography in 2006 reveals that the convergence of RET and OPC has also enabled a progressive selection and fine-tuning of Geometric Design Rules (GDR) at each technology node, based on systematic adoption of lithographic verification. This paper describes the use of "full-chip" lithography verification engines in current Design For Manufacturing (DFM) practices and extends the analysis to identify a set of key technologies and applications for the 45, 32 and 22 nm nodes. As OPC-derived tools enter the stage of maturity, from a software standpoint, their use-model is being greatly broadened from the back-end mask tape-out flow, upstream, directly integrated into physical design verification. Lithography awareness into the physical design environment, mediated by new DFM verification tools and flows, is driving various forms of manufacturable physical layout implementation: from Restricted Design Rules and Flexible Design Rules to Regular Circuit Fabrics. As new lithography solutions, such as immersion lithography and EUV, will have to be deployed within a complex technology framework, the paper also examines the trend towards "layout design regularization" and its implications for patterning and next generation lithographies.

From optical proximity correction to lithography-driven physical design (1996- 2006) : 10 years of resolution enhancement technology and the roadmap enablers for the next decade

Non-rectangular transistors in today's advanced processes pose a potential problem between manufacturing and design as today's compact transistor models have only one length and one width parameter to describe the gate dimensions. The transistor model is the critical link between manufacturing and design and needs to account for across gate CD variation as corner rounding along with other 2D proximity effects become more pronounced. This is a complex problem as threshold voltage and leakage current have a very complex non-linear relationship with gate length. There have been efforts trying to model non-rectangular gates as transistors in parallel, but this approach suffers from the lack of accurate models for "slice transistors", which could potentially necessitate new circuit simulators with new sets of complex equations. This paper will propose a new approach that approximates a non-rectangular transistor with an equivalent rectangular transistor and hence does not require a new transistor model or significant changes to circuit simulators. Effective length extraction consists of breaking a non-rectangular transistor into rectangular slices and then taking a weighted average based on simulated slice currents in HSPICE. As long as a different effective length is used for delay and static power analysis, simulation results show that the equivalent rectangular transistor behaves the same as a non-rectangular transistor.

From poly line to transistor : Building BSIM models for non- rectangular transistors

Design rule constraints (DRC) are the industry workhorse for constraining design to ensure both physical and electrical
manufacturability. However, as technology processes continue to shrink and aggressive resolution enhancement
technologies (RET) and optical proximity correction (OPC) are applied, standard DRC sometimes fails to fully capture
the concept of design manufacturability. Consequently, some DRC-clean layout designs are found to be difficult to
manufacture. Attempts have been made to "patch up" standard DRC with additional rules to identify these specific
problematic cases. However, due to the lack of specificity with DRC, these efforts often meet with mixed-success.
Although it typically resolves the issue at hand, quite often, it is the enforcement of some DRC rule that causes other
problematic geometries to be generated, as designers attempt to meet all the constraints given to them. In effect,
designers meet the letter of the law, as defined by the DRC implementation code, without understanding the "spirit of the
rule". This leads to more exceptional cases being added to the DRC manual, further increasing its complexity.
DRC Plus adopts a different approach. It augments standard DRC by applying fast 2D pattern matching to design layout
to identify problematic 2D configurations which are difficult to manufacture. The tool then returns specific feedback to
designers on how to resolve these issues. This basic approach offers several advantages over other DFM techniques: It is
enforceable, it offers a simple pass/no-pass criterion, it is simple to document as part of the design manual, it does not
require compute intensive simulations, and it does not require highly-accurate lithographic models that may not be
available during design. These advantages allow DRC Plus to be inserted early in the design flow, and enforced in
conjunction with standard DRC.

Luigi Capodieci

Papers

Modification of mask layout data to improve writeability of OPC

Characterization and synthesis of OPC structures by fourier space analysis and/or wavelet transform expansion

From optical proximity correction to lithography-driven physical design (1996- 2006) : 10 years of resolution enhancement technology and the roadmap enablers for the next decade

From poly line to transistor : Building BSIM models for non- rectangular transistors

DRC Plus: augmenting standard DRC with pattern matching on 2D geometries