Luigi Colombo

TL;DR: In this paper, a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides is described, the method comprising the steps of: depositing a first conductive material (114 of FIG. 7 d) on the top surface of the dielectrics layer and in the opening in the dieselayers to substantially fill the opening with the conductives, removing the portion of the first conductives located on the dieelayers, and removing a portion of those materials to recess to form a substantially plan

TL;DR: In this article, the authors describe a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG., 1) comprised of a Ferroelectric material on the bottom electrodes, the capacitance having a surface and side, and forming a top electrode (128 and 130 of FIG.).

TL;DR: In this paper, the authors proposed a capacitor structure for a semiconductor device which does not degrade by hydrogen or contamination, which consists of a lower electrode with a side surface and an upper front surface, a capacitor dielectric (126 of Fig.

TL;DR: In this article, a manufacturing method of a ferroelectric memory cell includes a step for forming on a certain structure, i.e., a dielectric layer 112 having therein a conductive contact 114, a bottom portion electrode 124 having a top surface and a plurality of side surfaces; a process for forming the barrier layers 118, 120 on the side surfaces of the bottom portion electrodes 124, the capacitor dielectrics 126, and the top portion electrode 128, 130; a stage for performing a heating step during a certain time in the atmosphere of a gas selected from the group

TL;DR: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with Fbased dielectrics etch and Cl- and F-based barrier etch as mentioned in this paper.