High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev

In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops (FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT), as well as the clock network (clock slope variations). For each topology, the variations of performance, robustness against hold violations, energy and leakage are statistically evaluated and compared. The impact of layout parasitics is explicitly included in the circuit design loop. The presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and estimates for early budgeting of variations before detailed circuit design. Also, the analysis enables a deeper understanding of the sensitivity to variations of existing topologies across a wide range of sizes and loads. In particular, this Part I introduces the methodology, the targeted flip-flop topologies and investigates the impact of process variations on flip-flop timing.

Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing

A 3-D network-on-chip (NoC) enables the design of high performance and low power many-core chips. Existing 3-D NoCs are inadequate for meeting the ever-increasing performance requirements of many-core processors since they are simple extensions of regular 2-D architectures and they do not fully exploit the advantages provided by 3-D integration. Moreover, the anticipated performance gain of a 3-D NoC-enabled many-core chip may be compromised due to the potential failures of through-silicon-vias that are predominantly used as vertical interconnects in a 3-D IC. To address these problems, we propose a machine-learning-inspired predictive design methodology for energy-efficient and reliable many-core architectures enabled by 3-D integration. We demonstrate that a small-world network-based 3-D NoC (3-D SWNoC) performs significantly better than its 3-D MESH-based counterparts. On average, the 3-D SWNoC shows 35% energy-delay-product improvement over 3-D MESH for the PARSEC and SPLASH2 benchmarks considered in this paper. To improve the reliability of 3-D NoC, we propose a computationally efficient spare-vertical link (sVL) allocation algorithm based on a state-space search formulation. Our results show that the proposed sVL allocation algorithm can significantly improve the reliability as well as the lifetime of 3-D SWNoC.

Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip

difficulty ofleakage estimation. Asdemonstrated in[3], leakage Inthis paper wepropose anovel projection-based algorithm to variations canreach 20x, while delays only varyabout 30%.Ithas estimate thefull-chip leakage powerwithconsideration ofboth also beenobserved that leakage powerissensitive tobothinterinter-die andintra-die process variations. Unlike manytraditional dieandintra-die variations. Intra-die variations modelthe approaches that rely onlog-Normal approximations, theproposed individual, butspatially correlated, local variations within the algorithm applies anovel projection method toextract alow-rank samedie. Theseintra-die variations mustbemodeled bymany quadratic model ofthelogarithm ofthefull-chip leakage current additional random variables, thereby significantly increasing the and,therefore, isnotlimited tolog-Normal distributions. By problem size ofleakage analysis. Forexample, thetotal number of exploring theunderlying sparse structure oftheproblem, an randomvariables canreach103106tomodelthefull-chip efficient algorithm isdeveloped toextract thenon-log-Normal variations forapractical industry design. leakage distribution withlinear computational complexity in Manyworkshavebeendeveloped tocapture theleakage circuit size. Inaddition, anincremental analysis algorithm is variations [4]-[10]. Mostofthese approaches approximate the proposed toquickly update theleakage distribution after changes leakage variation asalog-Normal distribution. Forthat purpose, a toacircuit aremade.Ournumerical examples inacommercialfirst-order (i.e., linear) Taylor expansion isusedtoapproximate 90nmCMOS process demonstrate that theproposed algorithmthelogarithm oftheleakage current. Given theincreasingly larger provides 4x errorreduction compared withthepreviouslyvariations innanoscale technologies, suchalinear approximation proposed log-Normal approximations, while achieving orders of canresult ininaccurate results, especially because theleakage magnitude moreefficiency thanaMonteCarlo analysis with104 current hasastrongly nonlinear dependency onprocess variations. samples. Aswill bedemonstrated bythenumerical examples inSection 4, a 20% estimation errorisobserved byusing thelinear Categories andSubject Descriptors

Projection-Based Statistical Analysis ofFull-Chip Leakage PowerwithNon-Log-Normal Distributions

In the context of high-performance computing, the integration of more computing capabilities with generic cores or dedicated accelerators for artificial intelligence (AI) application is raising more and more challenges. Due to the increasing costs of advanced nodes and the difficulties of shrinking analog and circuit input output signals (IOs), alternative architecture solutions to single die are becoming mainstream. Chiplet-based systems using 3D technologies enable modular and scalable architecture and technology partitioning. Nevertheless, there are still limitations due to chiplet integration on passive interposers—silicon or organic. In this article we present the first CMOS active interposer, integrating: 1) power management without any external components; 2) distributed interconnects enabling any chiplet-to-chiplet communication; and3) system infrastructure, design-for-test, and circuit IOs. The IntAct circuit prototype integrates six chiplets in FDSOI 28-nm technology, which are 3D-stacked onto this active interposer in 65-nm process, offering a total of 96 computing cores. Full scalability of the computing system is achieved using an innovative scalable cache-coherent memory hierarchy, enabled by distributed network-on-chips, with 3-Tbit/s/mm2 high bandwidth 3D-plug interfaces using 20- $\mu \text{m}$ pitch micro-bumps, 0.6-ns/mm low latency asynchronous interconnects, while the six chiplets are locally power-supplied with 156-mW/mm2 at 82%-peak-efficiency dc–dc converters through the active interposer. Thermal dissipation is studied showing the feasibility of such approach.

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IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management

With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article aims at comparing a set of representative static flip-flop architectures used in digital designs and at studying their sensitivity to process variations. Clock-to-Q delay, hold time and setup time means and standard deviations are compared for a low power 65 nm technology and commented. Then, a study of the hold/setup time failure probabilities according to the flip-flop used in a critical path is given to illustrate their robustness toward process variations.

/pdf/a-comparative-study-of-variability-impact-on-static-flip-gzfuzptnp7.pdf

A comparative study of variability impact on static flip-flop timing characteristics

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

To deal with variations, statistical methodologies can be completed by monitoring techniques implemented to cope with dynamic variations while keeping optimized operating points. This paper proposes a new monitoring structure, located in parallel of a pre-defined observable flip-flop. This structure, coupled with a specific detection window generation, embedded within the clock-tree, can anticipate timing violations to prevent system failures in real-time. Performances simulated in a 45 nm technology demonstrate a scalable, low power and low area cell which can be easily inserted in a standard CAD flow.

An innovative timing slack monitor for variation tolerant circuits

Three-dimensional stacking technology promises to solve the interconnect bottleneck problem by using Through-Silicon-Vias (TSVs) to vertically connect circuit layers. However, manufacturing steps may lead to partly broken or incompletely filled TSVs that may degrade the performance and reduce the useful lifetime of a 3D IC. Due to combinations of physical factors such as switching activity, supply noise and crosstalk, path delays can experience speed-up or slow-down that could let the effect of resistive open TSV go undetected by conventional test methods. In this work, we present a metric based on probabilistic analysis to detect delay defects induced by resistive opens that occur on signal line TSVs. Our experimental result will show the accuracy of the proposed metric.

Computing detection probability of delay defects in signal line tsvs

PVT monitors are mandatory to use tunable knobs designed to compensate the variability effects. This paper describes a new on-chip monitoring system, allowing failure anticipation in real-time, in looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of special structures situated near the flip-flops, coupled with a specific detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area fine-grain system, easily insertable in a standard CAD flow.

M. Belleville

Papers

A comparative study of variability impact on static flip-flop timing characteristics

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

An innovative timing slack monitor for variation tolerant circuits

Computing detection probability of delay defects in signal line tsvs

On-chip timing slack monitoring