This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

The emerging concept of multistandard radios calls for low-noise amplifier (LNA) solutions able to comply with their needs. Meanwhile, the increasing cost of scaled CMOS pushes towards low-area solutions in standard, digital CMOS. Feedback LNAs are able to meet both demands. This paper is devoted to the design of low-area active-feedback LNAs. We discuss the design of wideband, narrowband and multiband implementations. We demonstrate that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS

A 15.1 dB gain, 2.1 dB (min.) noise figure low-noise amplifier (LNA) fabricated in 0.13 mum CMOS operates across the entire 3.1-10.6 GHz ultrawideband (UWB). Noise figure variation over the band is limited to 0.43 dB. Reactive (transformer) feedback reduces the noise figure, stabilizes the gain, and sets the terminal impedances over the desired bandwidth. It also provides a means of separating ESD protection circuitry from the RF input path. Bias current-reuse limits power consumption of the 0.87mm2 IC to 9 mW from a 1.2 V supply. Comparable measured results are presented from both packaged and wafer probed test samples

A 1.2 V Reactive-Feedback 3.1–10.6 GHz Low-Noise Amplifier in 0.13 $\mu{\hbox {m}}$ CMOS

A noncoherent 0-16.7 Mb/s ultra-wideband (UWB) receiver using 3-5 GHz subbanded pulse-position modulation (PPM) signaling is implemented in a 90 nm CMOS process. The RF and mixed-signal baseband circuits operate at 0.65 V and 0.5 V, respectively. Using duty-cycling, adjustable bandpass filters, and a relative-compare baseband, the receiver achieves 2.5 nJ/bit at 10-3 BER with -99 dBm best case sensitivity at 100 kb/s. The energy efficiency is maintained across three orders of magnitude in data rate. For data rates less than 10 kb/s, leakage power dominates energy/bit.

A 2.5 nJ/bit 0.65 V Pulsed UWB Receiver in 90 nm CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.

A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS

The physical mechanisms that influence the triggering and holding voltage in a DMOS transistor in CMOS smart power technology are investigated. We demonstrate that a high and a low holding voltage device can be designed by changing the lateral bipolar base distance and that also the trigger voltage can be easily tuned. The layout variation that controls the holding voltage also leads to a different snapback mechanism and a different current flow through the device. Excellent ESD capabilities of 16-20 mA//spl mu/m width have been achieved.

https://ieeexplore.ieee.org/iel5/7356/19955/00922910.pdf

Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage

An improved calibration methodology for simultaneous capturing of voltage and current during an HBM pulse is presented. The capability of this new methodology for ESD protection device characterization and development is demonstrated using the quasi-static and transient response analysis of silicon-controlled rectifier devices.

Calibrated wafer-level HBM measurements for quasi-static and transient device analysis

A novel "plug-and-play" ESD protection methodology for wideband RF applications is demonstrated. This methodology utilizes an integrated transformer together with classical ESD protection elements. As a demonstrator, a wideband RF LNA in 0.18 mum CMOS is protected above 4.5 kV HBM without degrading its bandwidth.

T-diodes - a novel plug-and-play wideband RF circuit ESD protection methodology

This paper investigates on the transient pulse response of the device under test, which is becoming a critical aspect in determining the ESD reliability of a variety of technology products. For the first time, the feasibility to calibrate or tune the artifacts arising out of system parasitic to `see' the device transient response is presented in this paper with experimental data and numerical analysis.

M.I. Natarajan

Papers

A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS

Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage

Calibrated wafer-level HBM measurements for quasi-static and transient device analysis

T-diodes - a novel plug-and-play wideband RF circuit ESD protection methodology

Transient voltage overshoot in TLP testing — Real or artifact?