Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.

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Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

Scanning thermal microscopy is a scanning proximal probe technique, which can be used for mapping spatial variation of thermal properties of a surface such as temperature, thermal conductivity, and thermal diffusivity. The sensor presented here is a resistance based probe consisting of a nanometer-sized filament formed at the end of a piezoresistive atomic force microscope type cantilever. The freestanding filament is deposited by focused electron beam deposition using methylcyclopentadienyl trimethyl platinum as a precursor gas. The filament height is in the range of 2–5 μm, with typical “wire” diameters between 30 and 100 nm. Typical deposition times are between 2 and 5 min, and might be further shortened by optimizing the precursor gas flux. Because of its small size, the new probe has a high spatial resolution (<20 nm tip end radius) and, due to the low thermal mass, a high thermal sensitivity and fast response time. In this article, experiments designed to characterize the mechanical stability and el...

Novel high resolution scanning thermal probe

Non-uniform temperature profiles along global interconnect lines in high-performance ICs can significantly impact the performance of these lines. This paper presents a detailed analysis and modeling of the interconnect performance degradation due to non-uniform temperature profiles that exist along their lengths, which in turn arise due to the thermal gradients in the underlying substrate. A non-uniform temperature-dependent distributed RC interconnect delay model is proposed for the first time. The model has been applied to a wide variety of interconnect layouts and temperature distributions to quantify the impact on signal integrity issues including clock skew fluctuations.

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Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs

Multi-finger microcages with metal/diamond like carbon (DLC) bilayer and polymer/metal/DLC trilayer structures were analyzed, simulated and fabricated. Modelling by finite element analysis showed that a soft polymer can be used together with DLC to form a normally closed microcage which can be opened by 90° angle at a temperature of ∼400 K, which is much lower than that of a metal/DLC bilayer structure previously demonstrated. The opening temperature for a microcage is independent of the finger dimensions, but is simply determined by the thermal expansion coefficient difference of two materials used. Microcages with SU8/DLC bilayer and SU8/Al/DLC trilayer structures have been fabricated and fully closed microcages with diameters of ∼40 μm have been obtained. Initial electrical tests have showed these devices open by more than 90° at a temperature lower than 150 °C, roughly in agreement with the theoretical analysis.

Modelling and fabrication of low operation temperature microcages with a polymer/metal/DLC trilayer structure

Electromigration is caused by high current-density stress in the metallization patterns and is a major source of breakdown in electronic devices. It is, therefore, an important reliability issue to verify current densities within all stressed metallization patterns. In this paper, we propose an efficient methodology for hierarchical verification of current densities in arbitrarily shaped custom-circuit layouts as commonly used in analog circuits and analog blocks in mixed-signal ICs. Our approach includes a quasi-three-dimensional model to verify irregularities, such as vias and incorporates thermal simulation data to account for the temperature dependency of the electrical field configuration and the electromigration process. The described methodology, which can be integrated into any IC design flow as a design rule check, has been successfully tested and verified in commercial design flows.

/pdf/hierarchical-current-density-verification-in-arbitrarily-2k9lv2fzkr.pdf

Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits

Thermal characteristics of submicron vias strongly impact reliability of multilevel VLSI interconnects. The magnitude and spatial distribution of the temperature rise around a via are important to accurately estimate interconnect lifetime under electromigration (EM), which is temperature dependent. Localized temperature rise can cause stress gradients inside the via structures and can also lead to thermal failures under high current stress conditions, such as electrostatic discharge (ESD) events. This letter reports the first use of a novel thermometry technique, scanning Joule expansion microscopy, to study the steady state and dynamic thermal behavior of small geometry vias under sinusoidal and pulsed current stress. Measurement of the spatial distribution of temperature rise around a submicron via is reported with sub-0.1 /spl mu/m resolution, along with other thermal characteristics including the thermal time constant.

M. Igeta

Papers

Thermal characteristics of submicron vias studied by scanning Joule expansion microscopy