M
M. Jurdit
Publications - 8
Citations - 144
M. Jurdit is an academic researcher. The author has contributed to research in topics: Lithography & Photolithography. The author has an hindex of 6, co-authored 8 publications receiving 141 citations.
Papers
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Proceedings ArticleDOI
A conventional 45nm CMOS node low-cost platform for general purpose and low power applications
Frederic Boeuf,Franck Arnaud,M.T. Basso,D. Sotta,Francois Wacquant,J. Rosa,N. Bicais-Lepinay,H. Bernard,J. Bustos,S. Manakli,M. Gaillardin,J. Grant,Thomas Skotnicki,B. Tavel,B. Duriez,M. Bidaud,Pascal Gouraud,C. Chaton,Pierre Morin,J. Todeschini,M. Jurdit,Laurent Pain,V. DeJonghe,R. El-Farhane,S. Jullian +24 more
TL;DR: In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed and performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonstrated.
Proceedings ArticleDOI
Low cost 65nm CMOS platform for Low Power & General Purpose applications
Franck Arnaud,B. Duriez,B. Tavel,Laurent Pain,J. Todeschini,M. Jurdit,Y. Laplanche,Frederic Boeuf,F. Salvetti,Damien Lenoble,J.P. Reynard,Francois Wacquant,Pierre Morin,N. Emonet,D. Barge,M. Bidaud,D. Ceccarelli,P. Vannier,Y. Loquet,H. Leninger,F. Judong,C. Perrot,I. Guilmeau,R. Palla,A. Beverina,V. DeJonghe,M. Broekaart,V. Vachellerie,R.A. Bianchi,Bertrand Borot,T. Devoivre,N. Bicais,David Roy,M. Denais,K. Rochereau,R. Difrenza,Nicolas Planes,H. Brut,L. Vishnobulta,D. Reber,P. Stolk,M. Woo +41 more
TL;DR: A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution.
Proceedings ArticleDOI
Electron beam direct write lithography flexibility for ASIC manufacturing: an opportunity for cost reduction (Keynote Paper)
Laurent Pain,M. Jurdit,J. Todeschini,S. Manakli,B. Icard,Blandine Minghetti,G. Bervin,A. Beverina,Francois Leverd,M. Broekaart,Pascal Gouraud,V. De Jonghe,Ph. Brun,Stephane Denorme,Frederic Boeuf,V. Wang,Daniel Henry +16 more
TL;DR: In this paper, the authors highlight application examples where the advantages of this lithography solution are demonstrated for advanced research and development application with the patterning of 45 nm SRAM and for the fast validation of architecture designs.
Proceedings ArticleDOI
0.248/spl mu/m/sup 2/ and 0.334/spl mu/m/sup 2/ conventional bulk 6T-SRAM bit-cells for 45nm node low cost - general purpose applications
Frederic Boeuf,Franck Arnaud,C. Boccaccio,F. Salvetti,J. Todeschini,Laurent Pain,M. Jurdit,S. Manakli,B. Icard,Nicolas Planes,N. Gierczynski,Stephane Denorme,B. Borot,C. Ortolland,B. Duriez,B. Tavel,Pascal Gouraud,M. Broekaart,V. DeJonghe,P. Brun,F. Guyader,P. Morini,C. Reddy,M. Aminpur,C. Laviron,S. Smith,J.P. Jacquemin,M. Mellier,F. Andre,N. Bicais-Lepinay,S. Jullian,J. Bustos,Thomas Skotnicki +32 more
TL;DR: In this article, the authors highlight the realization and 0.248/spl mu/m/sup 2/ to 0.334/spl µ/m 2/ SRAM bit-cells with conventional bulk technology based on 19/spl Aring/CEN SiON gate oxide, poly-silicon gate electrode, and mobility enhancement techniques for both nMOS and pMOS.
Journal ArticleDOI
New electron beam proximity effects correction (EBPC) approach for 45nm and 32nm nodes
S. Manakli,K. Docherty,Laurent Pain,J. Todeschini,M. Jurdit,B. Icard,S. Leseuil,Blandine Minghetti +7 more
TL;DR: In this paper, a rule-based EBDW (E-beam direct write) correction was proposed to correct the smallest and most dense structures encountered in designs with features below 65nm.