S
Stephane Denorme
Researcher at STMicroelectronics
Publications - 51
Citations - 868
Stephane Denorme is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Metal gate & NMOS logic. The author has an hindex of 15, co-authored 51 publications receiving 811 citations. Previous affiliations of Stephane Denorme include Grenoble Institute of Technology.
Papers
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Journal ArticleDOI
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below
Claire Fenouillet-Beranger,Stephane Denorme,Pierre Perreau,C. Buj,O. Faynot,Francois Andrieu,L. Tosti,Sébastien Barnola,T. Salvetat,X. Garros,Mikael Casse,F. Allain,Nicolas Loubet,Loan Pham-Nguyen,E. Deloffre,Mickael Gros-Jean,Remi Beneyton,C. Laviron,M. Marin,C. Leyris,Sebastien Haendler,Francois Leverd,Pascal Gouraud,P. Scheiblin,L. Clement,Roland Pantel,Simon Deleonibus,Thomas Skotnicki +27 more
TL;DR: In this article, the authors compared Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP) conditions and compared them with bulk 45-nm technology in terms of variability and noise.
Proceedings ArticleDOI
Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm 2 6T-SRAM bitcell
Claire Fenouillet-Beranger,Stephane Denorme,B. Icard,F. Boeuf,J. Coignus,O. Faynot,L. Brevard,C. Buj,C. Soonekindt,J. Todeschini,J.C. Le-Denmat,N. Loubet,C. Gallon,P. Perreau,S. Manakli,B. Mmghetti,L. Pain,V. Arnal,A. Vandooren,D. Aime,L. Tosti,C. Savardi,F. Martin,T. Salvetat,S. Lhostis,C. Laviron,N. Auriac,T. Kormann,G. Chabanne,S. Gaillard,O. Belmont,E. Laffosse,D. Barge,A. Zauner,A. Tarnowka,K. Romanjec,H. Brut,A. Lagha,S. Bonnetier,F. Joly,N. Mayet,A. Cathignol,D. Galpin,D. Pop,R. Delsol,R. Pantel,F. Pionnier,G. Thomas,D. Bensahel,S. Deleombus,T. Skotnicki,H. Mmgam +51 more
TL;DR: This paper reports on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes and good performance for nMOS and pMOS transistors in the ultra-low-leakage regime.
Proceedings ArticleDOI
Efficient multi-V T FDSOI technology with UTBOX for low power circuit design
C. Fenouillet-Beranger,Olivier P. Thomas,P. Perreau,J.-P. Noel,A. Bajolet,Sebastien Haendler,L. Tosti,Sébastien Barnola,Remi Beneyton,C. Perrot,C. de Buttet,F. Abbate,F. Baron,B. Pernet,Y. Campidelli,L. Pinzelli,Pascal Gouraud,M. Casse,C. Borowiak,Olivier Weber,Francois Andrieu,Konstantin Bourdelle,Bich-Yen Nguyen,F. Boedt,Stephane Denorme,Frederic Boeuf,O. Faynot,Thomas Skotnicki +27 more
TL;DR: For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated and the effectiveness of back biasing for short devices in order to achieve I-ON current improvement by 45% for LVT options at an I-OFF current of 23nA/µm and a leakage reduction by 2 decades.
Journal ArticleDOI
Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below
C. Fenouillet-Beranger,Pierre Perreau,Stephane Denorme,L. Tosti,Francois Andrieu,Olivier Weber,Stephane Monfray,Sébastien Barnola,Christian Arvet,Y. Campidelli,Sebastien Haendler,Remi Beneyton,C. Perrot,C. de Buttet,P. Gros,Loan Pham-Nguyen,Francois Leverd,Pascal Gouraud,F. Abbate,F. Baron,A. Torres,C. Laviron,L. Pinzelli,J. Vetier,C. Borowiak,A. Margain,Daniel Delprat,F. Boedt,Konstantin Bourdelle,Bich-Yen Nguyen,O. Faynot,Tomasz Skotnicki +31 more
TL;DR: In this article, the impact of an ultra-thin box (UTBOX) with and without ground plane (GP) on a 32-nm fully-depleted SOI (FDSOI) high-k/metal gate technology is explored.
Proceedings ArticleDOI
Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
Claire Fenouillet-Beranger,Pierre Perreau,Loan Pham-Nguyen,Stephane Denorme,Francois Andrieu,L. Tosti,L. Brevard,Olivier Weber,Sébastien Barnola,T. Salvetat,X. Garros,Mikael Casse,Charles Leroux,Jean-Philippe Noel,Olivier P. Thomas,B. Le-Gratiet,F. Baron,Maxime Gatefait,Yves Campidelli,F. Abbate,C. Perrot,C. De-Buttet,Remi Beneyton,L. Pinzelli,Francois Leverd,Pascal Gouraud,Mickael Gros-Jean,A. Bajolet,Cecilia M. Mezzomo,C. Leyris,Sebastien Haendler,D. Noblet,R. Pantel,A. Margain,C. Borowiak,Emmanuel Josse,Nicolas Planes,D. Delprat,F. Boedt,K. Bourdelle,B.Y. Nguyen,Frederic Boeuf,O. Faynot,Thomas Skotnicki +43 more
TL;DR: In this article, the FD-SOI with High-K and Single Metal gate is presented as a possible candidate for LP multimedia technology, and a hybrid FDSOI/bulk co-integration with UTBOX is demonstrated for LP applications.