Models of insulating interfaces between (100)GaAs and HfO2, Gd2O3, and Al2O3 are constructed and used to host various interfacial defects to see which give rise to gap states. The antibonding state of As–As dimers is found to lie in the upper band gap and is identified as a possible major source of the interface gap states which cause Fermi level pinning in GaAs-oxide interfaces and field effect transistors.

Defect states at III-V semiconductor oxide interfaces

The authors model the capacitance-voltage (CV) behavior of In0.53Ga0.47As metal-oxide-semiconductor (MOS) structures and compare the results to experimental CV-curves. Due to the very low conduction band density of states, ideal III-V MOS structures should present an asymmetric CV behavior, with lower accumulation capacitance on the conduction band side. The absence of this asymmetric CV shape in experimental CV curves points toward the presence of additional states inside the conduction band at the oxide-semiconductor interface. Comparisons between the model and experimental data allow the determination and approximate quantification of a large acceptorlike interface state density above the conduction band edge energy.

On the interface state density at In0.53Ga0.47As/oxide interfaces

The role of spontaneous and piezoelectric polarization in III-V nitride heterostructure devices is discussed. Problems as well as opportunities in incorporating polarization in abrupt and graded heterojunctions composed of binary, ternary, and quaternary nitrides are outlined.

Polarization-Engineering in III-V Nitride Heterostructures: New Opportunities For Device Design

The need for high-κ gate dielectrics and metal gates in advanced integrated circuits has reopened the door to Ge and III–V compounds as potential replacements for silicon channels, offering the possibility to further increase the performances of complementary metal oxide semiconductor (CMOS) circuits, as well as adding new functionalities. Yet, a fundamental issue related to high-mobility channels in CMOS circuits is the electrical passivation of their interfaces (i.e., achieving a low density of interface defects) approaching state-of-the-art Si-based devices. Here we discuss promising approaches for the passivation of Ge and III–V compounds and highlight insights obtained by combining experimental characterization techniques with first-principles simulations.

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Surface Defects and Passivation of Ge and III–V Interfaces

This paper studies the effect of substrate-induced strain in the transport properties of AlGaN/GaN heterostructures grown on Si substrates by metal-organic chemical vapor deposition. Partial thinning of the original Si substrate by chemical dry etching has been used to induce controllable amounts of biaxial strain in the sample. After each etching step, Raman and Hall effect—Van Der Pauw measurements were performed as a function of remaining Si substrate thickness to study the residual biaxial strain and transport properties of the two-dimensional electron gas (2DEG). A 25% increase in the 2DEG density was obtained after removal of ∼30% of the total Si thickness. In addition, a 20% higher electron mobility has been observed under biaxial strain increase. This new technology has been applied to standard AlGaN/GaN transistors grown on Si substrates to increase their maximum current density by ∼20%.

Effect of substrate-induced strain in the transport properties of AlGaN/GaN heterostructures

Electrical properties of Ga2O3/GaAs interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm (0.9 les EOT les 3.9 nm) have been characterized by capacitance-voltage measurements. Midgap interface state density Dit, effective workfunction phim, fixed charge Qf, dielectric constant kappa, and low field leakage current density are 2 times1011 cm-2 middoteV-1, 4.93 eV, -8.9 times1011 cm-2, 19.5, and 10-9- 10-8 A/cm2, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.

M. Passlack

Papers

Electrical Properties of $\hbox{Ga}_{2}\hbox{O}_{3}/ \hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs