This paper presents a comparison of hot-carrier degradation experiments with simulations of hot electron and hole emission into the oxide. It is shown that both the emission of holes and of electrons are essential to explain the dominant generation of negative charge by a new degradation mechanism. Moreover, a peak of positive-charge generation at a gate voltage close to threshold was found in our experiments which is due to hole trapping. A simple degradation model based on the calculated electron and hole emission is presented which gives a very good description of the observed behavior of degradation effects.

Hot-electron and hole-emission effects in short n-channel MOSFET's

The conditions of hot-carrier stressing of n-MOS transistors have been studied in order to investigate the types of damage arising from the stressing in the gate voltage range V/sub d//2>or=V/sub g/>or=V/sub d/. Although a maximum in the V/sub t/ degradation is seen at V/sub g/=V/sub d//2, considerable stress damage occurs at higher gate voltages (at and around V/sub g/=V/sub d/). This stress damage obeys a different power law as a function of time than that which is seen at V/sub g/=V/sub d//2. Examination of the damage using dynamic stress experiments and alternate static injection phases suggests that the oxide-trapped charge (N/sub ox/) is mostly responsible for the damage at V/sub g/=V/sub d/, whereas the degradation at V/sub g/=V/sub d//2 arises from the interface state (N/sub ss/) creation. An examination of the gate current conditions shows that the oxide traps are created under conditions of maximum electronic gate current, suggesting that the hot electrons are responsible for the damage. Analysis of the time evolution of the damage suggests that the two types of damage (N/sub ox/ and N/sub ss/) can be seen during a single stressing, depending on the stress voltage conditions. >

Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2>or=V/sub g/<or=V/sub d/) during hot-carrier stressing of n-MOS transistors

The degradation of p-MOS transistors is shown to proceed logarithmically in time. A simple, analytic degradation model is proposed that fully accounts for this observation. The logarithmic time dependence originates from the logarithmic growth of a region of filled traps from the drain junction towards the source. On this basis, a reliable lifetime extrapolation is performed. >

Explanation and model for the logarithmic time dependence of p-MOSFET degradation

This letter shows that degradation after pulsed stress is enhanced over comparable static stress up to a factor 10 and that it is a sensitive function of the phase shift between gate and drain voltage pulses. All our results are satisfactorily explained by the assumption that hot holes can be stored and released under certain field conditions in a layer of shallow oxide traps near the interface. The results were achieved by applying independent pulses at gate and drain. It is shown that this new method enables decisive tests of degradation models and the measurement of critical time constants.

Degradation of n-MOS-Transistors after pulsed stress

Physical properties of both electron trapping and detrapping are identified to influence the degradation behavior of p-MOS transistors. Focusing on electron trapping first, we find as a decisive feature a spatially growing region of filled traps in the vicinity of the drain. Due to an exponential decrease of the electron injection current as a function of distance to the drain, its length grows logarithmically over time resulting in a logarithmic time dependence of the degradation. The logarithmic growth of this region is proven by means of charge-pumping experiments, whereas the logarithmic time dependence of the degradation itself is readily visible in the transistor current. Including electron-detrapping, the model permits a consistent description of both time- and bias-dependence of the degradation thereby leading to an improved expression for the lifetime of p-MOS transistors. >

A model for the time- and bias-dependence of p-MOSFET degradation

The spatial distribution (along the channel) of the oxide-trapped charge induced by hot electron injection in MOS transistors biased in saturation, is studied by means of two-dimensional device simulators. It is shown that hot electron trapping leads to a charge almost uniformly distributed over the region included between the points of channel pinch-off and zero transversal component of the surface electric field. A simplified analytic expression for the drain current in the triode operating region of the HE modified transistor is also given and found to be in reasonable agreement with experimental curves.

Hot electrons in MOS transistors: Lateral distribution of the trapped oxide charge

This brief shows how the asymmetrical behavior of hot-electron modified MOSFET's with respect to swapping of source and drain is due to two-dimensional effects taking place within the transition region separating the device channel from the terminal junctions. In particular experimental data concerning enhanced threshold-voltage shift, asymmetrical transconductance, anomalous body effect, as well as short-channel-like behavior exhibited by the stressed transistors, are presented and discussed.

M. Vanzi

Papers

Hot electrons in MOS transistors: Lateral distribution of the trapped oxide charge

Two-dimensional effects in hot-electron modified MOSFET's