Showing papers in "IEEE Transactions on Electron Devices in 1983"
TL;DR: In this article, the electron mobility data for both arsenic-and boron-doped silicon are presented in the high doping range, and it is shown that electron mobility is significantly lower in As-and Boron-Doped silicon for carrier concentrations higher than 1019cm-3.
Abstract: New carrier mobility data for both arsenic- and boron-doped silicon are presented in the high doping range. The data definitely show that the electron mobility in As-doped silicon is significantly lower than in P-doped silicon for carrier concentrations higher than 1019cm-3. By integrating these data with those previously published, empirical relationships able to model the carrier mobility against carrier concentration in the whole experimental range examined to date (about eight decades in concentration) for As-, P-, and B-doped silicon are derived. Different parameters in the expression for the n-type dopants provide differentiation between the electron mobility in As-and in P-doped silicon. Finally, it is shown that these new expressions, once implemented in the SUPREM II process simulator, lead to reduced errors in the simulation of the sheet resistance values.
908 citations
TL;DR: In this article, the charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI) MOSFETs is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived.
Abstract: The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO 2 ) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.
662 citations
TL;DR: In this article, it is shown that the voltage drop depends on the pH of the electrolyte and is determined by two parameters, the pH at the point of zero charge, and a sensitivity parameter which is introduced in this paper.
Abstract: All chemical sensors based upon the field-effect principle share a common quality. Their measurable properties can be described in terms of a flat-band voltage. The various terms in the expression of the flat-band voltage are described and discussed, and in particular the voltage drop at the insulator-electrolyte interface. It is shown that this voltage drop depends on the pH of the electrolyte and is determined by two parameters, the pH at the point of zero charge, and a sensitivity parameter which is introduced in this paper. These parameters are obtained from the site-dissociation model of the insulator-electrolyte interface, combined with the Gouy-Chapmann-Stern theory of the electrical double layer at this interface. The theoretical description is used to interpret experimental results obtained from insulators with widely different properties, namely SiO 2 and Al 2 O 3 .
541 citations
TL;DR: In this article, simple formulas for wiring capacitances in VLSI, including two-and/or three-dimensional effects, were proposed for a wide range of wire thickness, wire width, and interwire spacing.
Abstract: This paper proposes simple formulas for wiring capacitances in VLSI, including two- and/or three-dimensional effects. The accuracy of these formulas are practically sufficient for a wide range of wire thickness, wire width, and interwire spacing.
487 citations
TL;DR: This paper describes the numerical techniques used to solve the coupled system of nonlinear partial differential equations which model semiconductor devices, and the efficient solution of the resulting nonlinear and linear algebraic equations.
Abstract: This paper describes the numerical techniques used to solve the coupled system of nonlinear partial differential equations which model semiconductor devices. These methods have been encoded into our device simulation package which has successfully simulated complex devices in two and three space dimensions. We focus our discussion on nonlinear operator iteration, discretization and scaling procedures, and the efficient solution of the resulting nonlinear and linear algebraic equations. Our companion paper [13] discusses physical aspects of the model equations and presents results from several actual device simulations.
278 citations
TL;DR: In this paper, a numerical method for analyzing heterostructure semiconductor devices is described, where the macroscopic semiconductor equations for materials with position-dependent dielectric constant, bandgap, and densities-of-states are first cast into a form identical to that commonly used to model heavily doped semiconductors.
Abstract: A numerical method for analyzing heterostructure semiconductor devices is described. The macroscopic semiconductor equations for materials with position-dependent dielectric constant, bandgap, and densities-of-states are first cast into a form identical to that commonly used to model heavily doped semiconductors. Fermi-Dirac statistics are also included within this simple, Boltzmann-like formulation. Because of the similarity in formulation to that employed for heavily doped semiconductors, well-developed numerical techniques can be directly applied to heterostructure simulation. A simple one-dimensional, finite difference solution is presented. The accuracy of the numerical method is assessed by comparing numerical results with special-case, analytical solutions. Finally, we apply numerical simulation to two heterostructure devices: the heterostructure bipolar transistor (HBT) and the modulation doped field-effect transistor. The influence of a conduction band spike on the current-voltage characteristics of the HBT emitter-base junction is studied, and the variation with gate bias of the two-dimensional electron gas in a field-effect device is also investigated.
216 citations
TL;DR: A new and significantly more capable version of the process-simulation tool SUPREM III is described--SUPREM III--which incorporates process models suitable for VLSI device design, and for the first time, models multilayer structures.
Abstract: Over the past several years, the process-simulation tool SUPREM II has proven useful in the design and optimization of both bipolar and MOS technologies. This paper describes a new and significantly more capable version of the program--SUPREM III--which incorporates process models suitable for VLSI device design. This new version of the program is now generally available and should provide a powerful new tool in VLSI design. For the first time, the program models multilayer structures (up to five material layers). It also incorporates substantially upgraded diffusion, oxidation, ion implantation, and other process models. These models incorporate, where possible, recent thinking about underlying physical mechanisms. The program remains a one-dimensional simulator; extensions to two dimensions are discussed. This paper concentrates on the process models and their underlying physics; implementation issues are addressed elsewhere.
214 citations
TL;DR: The theory of the staircase avalanche photodiode (APD) is presented and recent results on a new class of APD's with enhanced ratio of ionization coefficients are reviewed in this paper.
Abstract: The theory of the staircase avalanche photodiode (APD) is presented and recent results on a new class of APD's with enhanced ratio of ionization coefficients are reviewed. The staircase APD consists of a multistage graded gap structure where only electrons ionize; the entire ionization energy is provided by large conduction band steps (dynodes). A general expression for the excess noise factor F in terms of the number of stages and the multiplication per stage is presented. For high ionization yields per dynode the F factor is near unity independently of the number of stages, implying virtually noise free multiplication at high gain similar to a photomultiplier. This cannot be achieved in a conventional APD at high gain even if one of the ionization coefficients is zero. A comparison between the noise behavior of the staircase APD and that of a phototube is also presented. A microscopic theory of the ionization yield γ is discussed; to obtain a high γ electrons must approach the dynode with an energy in the order of ten times the optical phonon energy. The possible problem of residual hole-initiated ionization is also discussed. Formulas for the electron and hole initiated multiplications are derived; from a measurement of these quantities one can directly obtain the ionization yield and the residual hole ionization coefficient. Experimental and theoretical results on other structures (superlattice, channeling, graded gap APD's) with high \alpha/\beta ratio are also reviewed and design considerations for a long-wavelength multilayer APD are presented.
210 citations
TL;DR: In this paper, a four-terminal microelectronic test structure and test method are described for electrically determining the degree of uniformity of the interfacial layer in metal-semiconductor contacts and for directly measuring interfacial contact resistance.
Abstract: A four-terminal microelectronic test structure and test method are described for electrically determining the degree of uniformity of the interfacial layer in metal-semiconductor contacts and for directly measuring the interfacial contact resistance. A two-dimensional resistor network model is used to obtain the relationship between the specific contact resistance and the measured interfacial contact resistance for contacts with a uniform interfacial layer. A new six-terminal test structure is used for the direct measurement of end contact resistance and the subsequent determination of front contact resistance. A methodology is described for reducing the effects of both contact-window mask misalignment and parasitic resistance associated with these measurements. Measurement results are given for 98.5-percent Al/1.5- percent Si and 100-percent Al contacts on n-type silicon.
187 citations
TL;DR: In this paper, a model describing I-V and C-V characteristics of modulation doped FET's is developed and used to predict the performance of Al x Ga 1-x As/GaAs FETs in good agreement with experimental results.
Abstract: A model describing I-V and C-V characteristics of modulation doped FET's is developed and used to predict the performance of Al x Ga 1-x As/GaAs FET's in good agreement with our experimental results. It is shown that the change in the Fermi energy with the gate voltage changes the effective separation between the gate and the two-dimensional electron gas by about 80 A. Current-voltage characteristics were calculated using a two piece as well as a three piece linear approximation for the electron velocity and compared with experimental results. At 300 K, the two piece model overestimates the current predicted by the three piece model only by approximately 10-20 percent. At 77 K, however, the three piece linear approximation for the velocity field characteristic should be used since the electron mobility decreases very abruptly at about 200 V/cm. The effect of the nonlinear source resistance is also discussed along with the gate-to-source and gate-to-drain capacitances, parameters of paramount importance in determining device performance. These capacitances are calculated as functions of gate-to-source and drain-to-source voltages below saturation.
176 citations
TL;DR: In this paper, the fabrication of 6H-SiC ingot single crystals with up to 20mm diam and 24mm length is described with a modified Lely method using a suitable seed crystal.
Abstract: The fabrication of 6H-SiC ingot single crystals with up to 20-mm diam and 24-mm length is described. Crystal growth was realized with a modified Lely method using a suitable seed crystal. The growth temperature was 2200°C to obtain preferential growth of the 6H-modification with 2.9-eV bandgap useful for blue light emitting silicon carbide diodes. It is the first time that 6H-SiC ingot crystals yielding substrates for the industrial production of devices based on this compound were obtained. With controlled Al doping of the crystal it was possible to fabricate blue light diodes with the highest quantum efficiency reported so far.
TL;DR: In this article, the hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFETs down to submicrometer channel lengths.
Abstract: Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.
TL;DR: In this paper, a simple model of inversion layer and accumulation layer mobilities in Si MOSFET's was presented, where the use of an effective normal field and a simple approximation for the temperature dependent quantum mechanically broadened channel layer width Permits the development of a versatile semi-empirical equation.
Abstract: We present a simple model of inversion layer and accumulation layer mobilities in Si MOSFET's. The use of an effective normal field and a simple approximation for the temperature dependent quantum mechanically broadened channel layer width Permits the development of a versatile semi-empirical equation. This equation provides good agreement with electron mobility data in the literature as a function of normal electric field, temperature, substrate doping, and fixed charge density. Screening effects have considerable influence in the model. Subthreshold behavior is predicted with reasonable accuracy. The model is also applicable at high tangential fields where mobility is reduced due to hot-carrier effects.
IBM1
TL;DR: In this article, the authors investigated the collection process of alpha-particle-generated charge in silicon devices and found that a strong drift field extends far beyond the original depletion layer, and funnels a large number of carriers into the struck node.
Abstract: Experimentally and by computer simulation, we have investigated the collection process of alpha-particle-generated charge in silicon devices. We studied the total charge collected and the transient characteristics of collection for various structures. Analytic results indicate that a strong drift field extends far beyond the original depletion layer, and funnels a large number of carriers into the struck node. This field-funneling component of charge collection is a strong function of substrate resistivity and bias voltage. It is relatively independent of the area of the struck device. The collection is less efficient for a small capacitance node. The funneling also occurred with a time delay when an alpha particle missed the field region by a short distance. Devices on an n-type substrate were also studied. They exhibit a similar funneling effect as the p-type substrate. The agreement between measurement and simulation is excellent. The impact on future VLSI design is discussed.
TL;DR: In this article, the deformable mirror device (DMD) is an X-Y array of deformable elements addressed by an underlying array of MOS transistors, and the architecture, operation, and experimental results are presented for a 128 × 128 DMD.
Abstract: The deformable mirror device (DMD) is an X-Y array of deformable mirror elements addressed by an underlying array of MOS transistors. Applications include optical information processing and projection displays. The architecture, operation, and experimental results are presented for a 128 × 128 DMD.
TL;DR: The most effective way to design VLSI device structures is to use sophisticated, complex two-dimensional and three-dimensional models, including several choices of variables, including the basic semiconductor equations.
Abstract: The most effective way to design VLSI device structures is to use sophisticated, complex two-dimensional (2D) and three-dimensional (3D) models. This paper and its companion [1] discusses the numerical simulation of such device models. Here we describe the basic semiconductor equations including several choices of variables. Our examples illustrate results obtained from finite-difference and finite-element implementations. We stress the necessary 3D calculations for small-size MOSFET's. Numerical results on inter-electrode capacitive coupling are included.
TL;DR: In this article, a mobility model for carriers in the MOS inversion layer is proposed, which assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law.
Abstract: A mobility model for carriers in the MOS inversion layer is proposed. The model assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law. Two-dimensional computer simulation combined with the present mobility model can predict experimental drain current within an error of ± 5 percent. The present model is applicable and suitable for designing short-channel MOSFET's, especially in the submicrometer range. The "saturation velocity" in the MOS inversion layer is also discussed, based on Thornber's scaling law. The saturation velocity, as determined from the calculated drain current in the same way as experimentalists have done, is 6.6 × 106cm/s. This is close to what has been claimed to be "saturation velocity in the inversion layer," and is about two-thirds of microscopic saturation velocity. This lower saturation velocity originates from the nonuniform field distribution in the test device, and, therefore, the experimentally reported saturation velocity in the MOS inversion layer is inferred to be a macroscopic average, rather than the microscopic drift velocity.
TL;DR: In this paper, low-pressure chemical vapor deposition of tungsten silicide has been done and the properties of the deposited films have been studied to determine the process compatibility and suitability to form gate electrodes and interconnections in MOS VLSI applications.
Abstract: Low-pressure chemical vapor deposition of tungsten silicide has been done and the properties of the deposited films have been studied to determine the process compatibility and suitability to form gate electrodes and interconnections in MOS VLSI applications. The silicide was deposited on single-crystal silicon and on oxidized silicon with and without a coating of polycrystalline silicon film. Auger analysis of the As-deposited films showed absence of any contaminants in it. X-ray diffraction and transmission electron microscopy showed that As-deposited films were microcrystalline with grains smaller than 30 A and upon annealing became polycrystalline WSi 2 with hexagonal structure at 500°C and tetragonal structure at or above 600°C with a corresponding decrease in resistivity from 600-900 µΩ . cm to 35-60 µΩ . cm depending upon anneal temperature and time. No appreciable change in the thickness of the silicide was found during the high-temperature anneals. Silicon-rich silicide films remained stable, smooth, and free of cracks through high-temperature anneals and oxidations, and their adherence to the wafer remained excellent. On the other hand, metal-rich films had overall inferior properties. Thermal oxidation of WSi 2 on polysilicon in dry oxygen in the temperature range of 900 to 1100°C was found to be similar to that of silicon except the linear regime of oxidation was extremely rapid and the entire process could be modeled by a parabolic equation X^{2) = Bt with an activation energy of 1.7 eV. MOS capacitors were fabricated with silicide and polycide gate electrodes. Polysilicon thickness variation from 0 to 5000 A had no adverse effect on the electrical characteristics or mechanical integrity of the devices. In all cases, low values of N f (1 × 1010-7 × 1010cm-2) and N it ( \sime 8 MV/cm) were obtained.
TL;DR: The thin-film properties of refractory metal silicides along with related VLSI process technology are reviewed in this article, where material considerations, including thinfilm deposition techniques, film structure, electrical properties, are covered.
Abstract: The thin-film properties of refractory metal silicides are reviewed along with related VLSI process technology. Material considerations, including thin-film deposition techniques, film structure, electrical properties, are covered. Single-level and composite gate structures implemented with these silicides are described. Thin-film processing-plasma etching, thermal oxidation, ion-beam-enhanced silicide formation, dopant implantation-of these materials is discussed from the perspective of VLSI compatibility. Characteristics of MOS devices and circuits using these silicides are reviewed.
TL;DR: In this paper, the authors investigated the transconductance degradation effect of thin-oxide FET's due to the finite inversion-layer capacitance and the decrease of electron mobility as the electric field increases.
Abstract: In this work we investigate the transconductance degradation effect which occurs in thin-oxide FET's due to the finite inversion-layer capacitance and to the decrease of the electron mobility as the electric field increases. Experimental capacitance and charge measurements are performed at room and at liquid-nitrogen temperature on 10-nm oxide FET's, and the data are compared with a classical and a quantum-mechanical model extended to take into account the non-uniform doping profile in the silicon substrate. Accurate mobility determinations are performed accounting for the nonuniform distribution of the mobile charge along the channel, and a mobility expression against the average normal field is incorporated in a generalized Pao-Sah double-integral formula for the FET drain current. Design trade-offs for submicrometer FET's are finally discussed.
TL;DR: In this article, a physical model that describes the effects of grain boundaries on the linear-region (strong-inversion) channel conductance of SOI (polysilicon on silicon-dioxide) MOSFET's is developed and supported experimentally.
Abstract: A physical model that describes the effects of grain boundaries on the linear-region (strong-inversion) channel conductance of SOI (polysilicon on silicon-dioxide) MOSFET's is developed and supported experimentally. The model predicts an effective turn-on characteristic that occurs beyond the strong-inversion threshold, and henceforth defines the "carrier mobility threshold voltage" and the effective field-effect carrier mobility in the channel, which typically is higher than the actual (intragrain) mobility. These parameters, which are defined by the properties of the grain boundaries, can easily be misinterpreted experimentally as the threshold voltage and the actual carrier mobility.
IBM1
TL;DR: In this paper, a quantitative trapping model is introduced to describe the electrical properties of a semiconductor-grain-boundary-semiconductor (SGBS) barrier in polysilicon films over a wide temperature range.
Abstract: A quantitative trapping model is introduced to describe the electrical properties of a semiconductor-grain-boundary-semiconductor (SGBS) barrier in polysilicon films over a wide temperature range. The grain-boundary scattering effects on carrier transport are studied analytically by examining the behavior of the height and width of a rectangular grain-boundary potential barrier. The model also verifies the applicability of a single-crystal band diagram for the crystallite within which an impurity level exists. Carder transport includes not only thermionic field emission through the space-charge potential barrier resulting from trapping effects and through the grain-boundary scattering potential barrier but also thermionic emission over these barriers. Thermionic emission dominates at high temperatures; however, at low temperatures, thermionic field emission becomes more important and the grain-boundary scattering effects are an essential factor. By characterizing the experimental data of the I-V characteristics, resistivity, mobility, and carrier concentration, this model enhances the understanding of the current transport in polysilicon films with grain sizes from 100 A to 1 µm, doping levels from 1 × 1016to 8 × 1019cm-3, and measurement temperatures from -176 to 144°C. The limitations of the model are also discussed.
TL;DR: In this article, various mechanisms responsible for temperature sensitivity in silicon piezoresistive pressure sensors are described, including resistor match, oxide stress and junction leakage current playing relatively minor roles over the -40 to + 180°C temperature range.
Abstract: The various mechanisms responsible for temperature sensitivity in silicon piezoresistive pressure sensors are described. As a representative transducer, a full-bridge device having a 1-mm-square 23-µm-thick diaphragm is used. The 200 Ω/square, 2K-Ω bridge resistors produce a pressure sensitivity of 13.3 µV/V.mmHg with a temperature coefficient of -1300 ppm/°C. Variability in this sensitivity is most strongly influenced by the diaphragm thickness and the absolute resistor tolerance. A new technique-the electrochemical EDP etch-stop-is found to offer significant advantages over alternative schemes for diaphragm formation. Temperature sensitivity in electrostatically-bonded, vacuum-sealed devices is dominated by resistor match, with oxide stress and junction leakage current playing relatively minor roles over the -40 to + 180°C temperature range. While individual pressure trims for offset and sensitivity will continue to be required, individual temperature trims may be eliminated in these devices for many applications as increasingly precise resistor processes are used.
TL;DR: In this article, a scaled-down metaloxide-nitride-oxide-semiconductor (MONOS) structure is proposed to realize an extremely low-voltage programmable device.
Abstract: Theoretical and experimental investigations to obtain lower voltage electrically erasable and programmable ROM's (EEPROM's) than conventional devices have been performed. The scaled-down metal-oxide-nitride-oxide-semiconductor (MONOS) structure is proposed to realize an extremely low-voltage programmable device. The proposed scaled-down MONOS devices enjoy several advantages over MNOS devices, e.g., enlargement of the memory window, elimination of degradation phenomena, and drastic improvement in device yield. Low-voltage operation with ± 6-V supplies is demonstrated by the fabricated scaled-down MONOS transistors.
TL;DR: A complete set of parameters for any arbitrary model is estimated by a modified Levenberg-Marquardt method operating in linear constrained space, and the result is a nonlinear least-squares fit of the data to a set of width/length-measured device characteristics.
Abstract: VLSI circuit simulation necessitates specification of model parameters. For the device equations to predict the measured I-V characteristics, the extraction of these parameters is required, and conventionally, measurements are performed sequentially to determine one or a few parameter values. These procedures are specialized to a particular model, and neglect the parameter interaction, as well as they are performed on a device-by-device basis. In this paper, a complete set of parameters for any arbitrary model is estimated by a modified Levenberg-Marquardt method operating in linear constrained space, and the result is a nonlinear least-squares fit of the data to a set of width/length-measured device characteristics. This model-independent extraction approach is enhanced by a sensitivity analysis to check for redundant parameters and is implemented in the SUXES computer program. It has proved to be an effective tool for device characterization and for the development and evaluation of new models.
TL;DR: A novel discretization scheme, called "finite boxes," allows an optimal grid-point allocation and can be applied to nonrectangular devices and the advantages and computer resource savings of the new method are described by the simulation of a 100-V diode.
Abstract: A two-dimensional numerical device-simulation system is presented. A novel discretization scheme, called "finite boxes," allows an optimal grid-point allocation and can be applied to nonrectangular devices. The grid is generated automatically according to the specified device geometry. It is adapted automatically during the solution process by equidistributing a weight function which describes the local discretization error. A modified Newton method is used for solving the discretized nonlinear system. To achieve high flexibility the physical parameters can be defined by user-supplied models. This approach requires numerical calculation of parts of the coefficients of the Jacobian. Supplementary algorithms speed up convergence and inhibit the commonly known Newton overshoot. The advantages and computer resource savings of the new method are described by the simulation of a 100-V diode. We also present results for thyristor and GaAs MESFET simulations.
TL;DR: In this paper, the feasibility of double diffused drain is investigated comparing it with a conventional As drain over a wide range of effective channel length from 0.5 to 5 µm.
Abstract: An As-P(n+-n-) double diffused drain is characterized as one of the most feasible device structures for VLSI's from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.
TL;DR: Bell Integrated Circuit Engineering Process Simulator (BICEPS) is a comprehensive VLSI process-simulation program developed at Bell Laboratories BICEPS incorporates the most up-to-date physical models and efficient numerical algorithms to make it a highly robust and general-purpose program as discussed by the authors.
Abstract: Bell Integrated Circuit Engineering Process Simulator (BICEPS) is a comprehensive VLSI process-simulation program developed at Bell Laboratories BICEPS incorporates the most up-to-date physical models and efficient numerical algorithms to make it a highly robust and general-purpose program BICEPS can calculate doping profiles resulting from ion implantation, predeposition, oxidation, and epitaxy in one or two spatial dimensions as well as etching and deposition of oxide, nitride, and photoresist In this paper, the physics of IC process simulation will be reviewed with an emphasis on the various physical models implemented in BICEPS Calculation of the impurity profiles in VLSI devices involves the solution of a coupled set of nonlinear time-dependent partial differential equations, with moving boundaries and in more than one spatial dimension The numerical techniques in obtaining a solution to this problem, namely, spatial discretization, time discretization, and the treatment of moving boundaries are also described in this paper The capabilities of BICEPS are illustrated by the results of simulation of the fabrication of a typical NMOS transistor
IBM1
TL;DR: In this paper, the authors present an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure.
Abstract: This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure. Not only does the model describe the conditions for transient latchup, but it also predicts a previously unreported phenomenon of dynamic recovery, which we have verified experimentally. Compact Stability criteria are presented for the p-n-p-n structure that delineate the roles of ramp rate and circuit parameters.
TL;DR: The techniques used in relaxation-based electrical simulation are presented in a rigorous and unified framework, and the numerical properties of the various methods are explored.
Abstract: Circuit simulation programs have proven to be most important computer-aided design tools for the analysis of the electrical performance of integrated circuits. One of the most common analyses performed by circuit simulators and the most expensive in terms of computer time is nonlinear time-domain transient analysis. Conventional circuit simulators were designed initially for the cost-effective analysis of circuits containing a few hundred transistors or less. Because of the need to verify the performance of larger circuits, many users have successfully simulated circuits containing thousands of transistors despite the cost. Recently, a new class of algorithms has been applied to the electrical IC simulation problem. New simulators using these methods provide accurate waveform information with up to two orders of magnitude speed improvement for large circuits. These programs use relaxation methods for the solution of the set of ordinary differential equations, which describe the circuit under analysis, rather than the direct sparse-matrix methods on which standard circuit simulators are based. In this paper, the techniques used in relaxation-based electrical simulation are presented in a rigorous and unified framework, and the numerical properties of the various methods are explored. Both the advantages and the limitations of these techniques for the analysis of large IC's are described.