We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

/pdf/x-masking-during-logic-bist-and-its-impact-on-defect-18wu1pv6cj.pdf

X-masking during logic BIST and its impact on defect coverage

A new X-tolerant multiple-input signature register (MISR) compaction methodology is proposed which can compact output streams containing unknown (X) values. Unlike conventional X-masking approaches, it does not require any masking logic at the input of the MISR. Instead it uses symbolic simulation to express each bit of the MISR signature as a linear equation in terms of the X's. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and XORed together using a programmable XOR to cancel out all X values thereby yielding deterministic values that are invariant of what the final values of the X's end up being during the test. These X-canceled values can be compacted in a separate MISR to generate a final X-free signature. Each intermediate signature for an m-bit MISR can tolerate k X's present anywhere in the output stream with error detection capability equivalent to using an m-k bit MISR with no unknowns. The tester storage requirement is a small constant times the total number of unknowns in the test set and thus does not depend on the scan architecture, the number of test vectors, or the distribution of X's which is a key advantage compared with other X-tolerant compaction schemes.

https://users.ece.utexas.edu/~touba/research/itc07.pdf

X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISR

In this paper, we propose a new programmable deterministic built-in self-Test (BIST) method that requires significantly lower storage for deterministic patterns than existing programmable methods and provides high flexibility for test engineering in both internal and external test. Theoretical analysis suggests that significantly more care bits can be encoded in the seed of a linear feedback shift register (LFSR), if a limited number of conflicting equations is ignored in the employed linear equation system. The ignored care bits are separately embedded into the LFSR pattern. In contrast to known deterministic BIST schemes based on test set embedding, the embedding logic function is not hardwired. Instead, this information is stored in memory using a special compression and decompression method. Experiments for benchmark circuits and industrial designs demonstrate that the approach has considerably higher overall coding efficiency than the existing methods.

Programmable deterministic Built-In Self-Test

Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

On-chip comparison and response collection tools and techniques

The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution

X-Press Compactor for 1000x Reduction of Test Data

Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.

/pdf/efficient-pattern-mapping-for-deterministic-logic-bist-4empeuueqa.pdf

M. Wittke

Papers

X-masking during logic BIST and its impact on defect coverage

Efficient pattern mapping for deterministic logic BIST